Fault-tolerant parallel processing with real-time error detection and recovery

Chung Ho Chen; Arun K. Somani

doi:10.1109/ACSSC.1992.269071

Fault-tolerant parallel processing with real-time error detection and recovery

Chung Ho Chen, Arun K. Somani

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The performance of parallel processing for real-time application is very sensitive to the reliability of the system. This paper presents a unique error recovery mechanism based on new cache states, verified and non-verified, to detect and recover errors produced by the processor or cache memory or both due to transient faults. The proposed scheme remedies the insufficiency of the error-correcting code when facing with processor transient fault. This cache-based recovery metkod not only recovers errors in a local cache memory but also prevents the propagation of errors to other caches. We show that this new error recovery scheme can be easily integrated with existing cache coherency protocols.

Original language	English
Title of host publication	Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992
Publisher	IEEE Computer Society
Pages	994-998
Number of pages	5
ISBN (Electronic)	0818631600
DOIs	https://doi.org/10.1109/ACSSC.1992.269071
Publication status	Published - 1992
Event	26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992 - Pacific Grove, United States Duration: 1992 Oct 26 → 1992 Oct 28

Publication series

Name	Conference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)	1058-6393

Conference

Conference	26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992
Country/Territory	United States
City	Pacific Grove
Period	92-10-26 → 92-10-28

All Science Journal Classification (ASJC) codes

Signal Processing
Computer Networks and Communications

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10.1109/ACSSC.1992.269071

Cite this

Chen, C. H., & Somani, A. K. (1992). Fault-tolerant parallel processing with real-time error detection and recovery. In Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992 (pp. 994-998). Article 269071 (Conference Record - Asilomar Conference on Signals, Systems and Computers). IEEE Computer Society. https://doi.org/10.1109/ACSSC.1992.269071

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title = "Fault-tolerant parallel processing with real-time error detection and recovery",

abstract = "The performance of parallel processing for real-time application is very sensitive to the reliability of the system. This paper presents a unique error recovery mechanism based on new cache states, verified and non-verified, to detect and recover errors produced by the processor or cache memory or both due to transient faults. The proposed scheme remedies the insufficiency of the error-correcting code when facing with processor transient fault. This cache-based recovery metkod not only recovers errors in a local cache memory but also prevents the propagation of errors to other caches. We show that this new error recovery scheme can be easily integrated with existing cache coherency protocols.",

author = "Chen, {Chung Ho} and Somani, {Arun K.}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992 ; Conference date: 26-10-1992 Through 28-10-1992",

year = "1992",

doi = "10.1109/ACSSC.1992.269071",

language = "English",

series = "Conference Record - Asilomar Conference on Signals, Systems and Computers",

publisher = "IEEE Computer Society",

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}

Chen, CH & Somani, AK 1992, Fault-tolerant parallel processing with real-time error detection and recovery. in Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992., 269071, Conference Record - Asilomar Conference on Signals, Systems and Computers, IEEE Computer Society, pp. 994-998, 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992, Pacific Grove, United States, 92-10-26. https://doi.org/10.1109/ACSSC.1992.269071

Fault-tolerant parallel processing with real-time error detection and recovery. / Chen, Chung Ho; Somani, Arun K.
Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992. IEEE Computer Society, 1992. p. 994-998 269071 (Conference Record - Asilomar Conference on Signals, Systems and Computers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - The performance of parallel processing for real-time application is very sensitive to the reliability of the system. This paper presents a unique error recovery mechanism based on new cache states, verified and non-verified, to detect and recover errors produced by the processor or cache memory or both due to transient faults. The proposed scheme remedies the insufficiency of the error-correcting code when facing with processor transient fault. This cache-based recovery metkod not only recovers errors in a local cache memory but also prevents the propagation of errors to other caches. We show that this new error recovery scheme can be easily integrated with existing cache coherency protocols.

AB - The performance of parallel processing for real-time application is very sensitive to the reliability of the system. This paper presents a unique error recovery mechanism based on new cache states, verified and non-verified, to detect and recover errors produced by the processor or cache memory or both due to transient faults. The proposed scheme remedies the insufficiency of the error-correcting code when facing with processor transient fault. This cache-based recovery metkod not only recovers errors in a local cache memory but also prevents the propagation of errors to other caches. We show that this new error recovery scheme can be easily integrated with existing cache coherency protocols.

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ER -

Fault-tolerant parallel processing with real-time error detection and recovery

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