FFT Butterfly Network Design for Easy Testing

Cheng Wen Wu; Chen Ti Chang

doi:10.1109/82.219841

FFT Butterfly Network Design for Easy Testing

Cheng Wen Wu, Chen Ti Chang

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

We consider off-line testing and easily testable design of butterfly networks for fast Fourier transform. The butterfly networks are shown to be testable with 32 patterns using a design-for-testability technique based on the M-testability conditions. The functional-level cell-fault model is assumed, and the fault coverage for combinational single cell faults is 100%. A higher-level fault model-the module-fault model-is also discussed. We present a novel input-assignment technique based on the functional byectivity property of the butterfly modules to discover faults other than the cell faults (e.g., interconnection faults).

Original language	English
Pages (from-to)	110-115
Number of pages	6
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	40
Issue number	2
DOIs	https://doi.org/10.1109/82.219841
Publication status	Published - 1993 Jan 1

All Science Journal Classification (ASJC) codes

Signal Processing
Electrical and Electronic Engineering

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10.1109/82.219841

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