First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure

X. R. Yu; C. C. Hsieh; M. H. Chuang; M. Y. Chiu; T. C. Sun; W. Z. Geng; W. H. Chang; Y. J. Shih; W. H. Lu; W. C. Chang; Y. C. Lin; Y. C. Pai; C. Y. Lai; M. H. Chuang; Y. Dei; C. Y. Yang; H. Y. Lu; N. C. Lin; C. T. Wu; K. H. Kao; W. C.Y. Ma; D. D. Lu; Y. J. Lee; G. L. Luo; M. H. Chiang; T. Maeda; W. F. Wu; Y. M. Li; T. H. Hou

doi:10.1109/IEDM45741.2023.10413801

First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure

X. R. Yu, C. C. Hsieh, M. H. Chuang, M. Y. Chiu, T. C. Sun, W. Z. Geng, W. H. Chang, Y. J. Shih, W. H. Lu, W. C. Chang, Y. C. Lin, Y. C. Pai, C. Y. Lai, M. H. Chuang, Y. Dei, C. Y. Yang, H. Y. Lu, N. C. Lin, C. T. Wu, K. H. KaoW. C.Y. Ma, D. D. Lu, Y. J. Lee, G. L. Luo, M. H. Chiang, T. Maeda, W. F. Wu, Y. M. Li, T. H. Hou

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This work presents experimental electrical characteristics and circuit prediction at cryogenic temperatures (down to 10 K) for three different kinds of germanium (Ge)-based FETs with advanced Fin/GAA structures. Among them, the layer transferred Ge-on-Insulator (GeOI) FinFET significantly improves its I-V characteristic during cryogenic measurements, such as a steeper subthreshold swing at 10K and a better I_on. The developed GeOI fabrication method provides an effective way to eliminate the defects originating from misfit dislocations at the Ge/Si substrate during epitaxial growth, which would be treated as the key to device performance enhancement under 10 K. According to the measured IV at 10 K and circuit prediction, GeOI FinFETs with high Ge crystallinity are strong candidates for High-Performance-Computing (HPC) applications.

Original language	English
Title of host publication	2023 International Electron Devices Meeting, IEDM 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350327670
DOIs	https://doi.org/10.1109/IEDM45741.2023.10413801
Publication status	Published - 2023
Event	2023 International Electron Devices Meeting, IEDM 2023 - San Francisco, United States Duration: 2023 Dec 9 → 2023 Dec 13

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2023 International Electron Devices Meeting, IEDM 2023
Country/Territory	United States
City	San Francisco
Period	23-12-09 → 23-12-13

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM45741.2023.10413801

Cite this

Yu, X. R., Hsieh, C. C., Chuang, M. H., Chiu, M. Y., Sun, T. C., Geng, W. Z., Chang, W. H., Shih, Y. J., Lu, W. H., Chang, W. C., Lin, Y. C., Pai, Y. C., Lai, C. Y., Chuang, M. H., Dei, Y., Yang, C. Y., Lu, H. Y., Lin, N. C., Wu, C. T., ... Hou, T. H. (2023). First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure. In 2023 International Electron Devices Meeting, IEDM 2023 (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM45741.2023.10413801

Yu, X. R. ; Hsieh, C. C. ; Chuang, M. H. et al. / First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure. 2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{2c485cafeee24718bdf496e2643e2284,

title = "First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure",

abstract = "This work presents experimental electrical characteristics and circuit prediction at cryogenic temperatures (down to 10 K) for three different kinds of germanium (Ge)-based FETs with advanced Fin/GAA structures. Among them, the layer transferred Ge-on-Insulator (GeOI) FinFET significantly improves its I-V characteristic during cryogenic measurements, such as a steeper subthreshold swing at 10K and a better Ion. The developed GeOI fabrication method provides an effective way to eliminate the defects originating from misfit dislocations at the Ge/Si substrate during epitaxial growth, which would be treated as the key to device performance enhancement under 10 K. According to the measured IV at 10 K and circuit prediction, GeOI FinFETs with high Ge crystallinity are strong candidates for High-Performance-Computing (HPC) applications.",

author = "Yu, {X. R.} and Hsieh, {C. C.} and Chuang, {M. H.} and Chiu, {M. Y.} and Sun, {T. C.} and Geng, {W. Z.} and Chang, {W. H.} and Shih, {Y. J.} and Lu, {W. H.} and Chang, {W. C.} and Lin, {Y. C.} and Pai, {Y. C.} and Lai, {C. Y.} and Chuang, {M. H.} and Y. Dei and Yang, {C. Y.} and Lu, {H. Y.} and Lin, {N. C.} and Wu, {C. T.} and Kao, {K. H.} and Ma, {W. C.Y.} and Lu, {D. D.} and Lee, {Y. J.} and Luo, {G. L.} and Chiang, {M. H.} and T. Maeda and Wu, {W. F.} and Li, {Y. M.} and Hou, {T. H.}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International Electron Devices Meeting, IEDM 2023 ; Conference date: 09-12-2023 Through 13-12-2023",

year = "2023",

doi = "10.1109/IEDM45741.2023.10413801",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 International Electron Devices Meeting, IEDM 2023",

address = "United States",

}

Yu, XR, Hsieh, CC, Chuang, MH, Chiu, MY, Sun, TC, Geng, WZ, Chang, WH, Shih, YJ, Lu, WH, Chang, WC, Lin, YC, Pai, YC, Lai, CY, Chuang, MH, Dei, Y, Yang, CY, Lu, HY, Lin, NC, Wu, CT, Kao, KH, Ma, WCY, Lu, DD, Lee, YJ, Luo, GL, Chiang, MH, Maeda, T, Wu, WF, Li, YM & Hou, TH 2023, First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure. in 2023 International Electron Devices Meeting, IEDM 2023. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., 2023 International Electron Devices Meeting, IEDM 2023, San Francisco, United States, 23-12-09. https://doi.org/10.1109/IEDM45741.2023.10413801

First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure. / Yu, X. R.; Hsieh, C. C.; Chuang, M. H. et al.
2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure

AU - Yu, X. R.

AU - Hsieh, C. C.

AU - Chuang, M. H.

AU - Chiu, M. Y.

AU - Sun, T. C.

AU - Geng, W. Z.

AU - Chang, W. H.

AU - Shih, Y. J.

AU - Lu, W. H.

AU - Chang, W. C.

AU - Lin, Y. C.

AU - Pai, Y. C.

AU - Lai, C. Y.

AU - Chuang, M. H.

AU - Dei, Y.

AU - Yang, C. Y.

AU - Lu, H. Y.

AU - Lin, N. C.

AU - Wu, C. T.

AU - Kao, K. H.

AU - Ma, W. C.Y.

AU - Lu, D. D.

AU - Lee, Y. J.

AU - Luo, G. L.

AU - Chiang, M. H.

AU - Maeda, T.

AU - Wu, W. F.

AU - Li, Y. M.

AU - Hou, T. H.

PY - 2023

Y1 - 2023

N2 - This work presents experimental electrical characteristics and circuit prediction at cryogenic temperatures (down to 10 K) for three different kinds of germanium (Ge)-based FETs with advanced Fin/GAA structures. Among them, the layer transferred Ge-on-Insulator (GeOI) FinFET significantly improves its I-V characteristic during cryogenic measurements, such as a steeper subthreshold swing at 10K and a better Ion. The developed GeOI fabrication method provides an effective way to eliminate the defects originating from misfit dislocations at the Ge/Si substrate during epitaxial growth, which would be treated as the key to device performance enhancement under 10 K. According to the measured IV at 10 K and circuit prediction, GeOI FinFETs with high Ge crystallinity are strong candidates for High-Performance-Computing (HPC) applications.

AB - This work presents experimental electrical characteristics and circuit prediction at cryogenic temperatures (down to 10 K) for three different kinds of germanium (Ge)-based FETs with advanced Fin/GAA structures. Among them, the layer transferred Ge-on-Insulator (GeOI) FinFET significantly improves its I-V characteristic during cryogenic measurements, such as a steeper subthreshold swing at 10K and a better Ion. The developed GeOI fabrication method provides an effective way to eliminate the defects originating from misfit dislocations at the Ge/Si substrate during epitaxial growth, which would be treated as the key to device performance enhancement under 10 K. According to the measured IV at 10 K and circuit prediction, GeOI FinFETs with high Ge crystallinity are strong candidates for High-Performance-Computing (HPC) applications.

UR - http://www.scopus.com/inward/record.url?scp=85185580492&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85185580492&partnerID=8YFLogxK

U2 - 10.1109/IEDM45741.2023.10413801

DO - 10.1109/IEDM45741.2023.10413801

M3 - Conference contribution

AN - SCOPUS:85185580492

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2023 International Electron Devices Meeting, IEDM 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 International Electron Devices Meeting, IEDM 2023

Y2 - 9 December 2023 through 13 December 2023

ER -

Yu XR, Hsieh CC, Chuang MH, Chiu MY, Sun TC, Geng WZ et al. First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure. In 2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM45741.2023.10413801

First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure

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