First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications

S. W. Chang; T. H. Lu; C. Y. Yang; C. J. Yeh; M. K. Huang; C. F. Meng; P. J. Chen; T. H. Chang; Y. S. Chang; J. W. Jhu; T. Z. Hong; C. C. Ke; X. R. Yu; W. H. Lu; M. A. Baig; T. C. Cho; P. J. Sung; C. J. Su; F. K. Hsueh; B. Y. Chen; H. H. Hu; C. T. Wu; K. L. Lin; W. C.Y. Ma; D. D. Lu; K. H. Kao; Y. J. Lee; C. L. Lin; K. P. Huang; K. M. Chen; Y. Li; S. Samukawa; T. S. Chao; G. W. Huang; W. F. Wu; W. H. Lee; J. Y. Li; J. M. Shieh; J. H. Tarng; Y. H. Wang; W. K. Yeh

doi:10.1109/IEDM19574.2021.9720675

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications

S. W. Chang, T. H. Lu, C. Y. Yang, C. J. Yeh, M. K. Huang, C. F. Meng, P. J. Chen, T. H. Chang, Y. S. Chang, J. W. Jhu, T. Z. Hong, C. C. Ke, X. R. Yu, W. H. Lu, M. A. Baig, T. C. Cho, P. J. Sung, C. J. Su, F. K. Hsueh, B. Y. ChenH. H. Hu, C. T. Wu, K. L. Lin, W. C.Y. Ma, D. D. Lu, K. H. Kao, Y. J. Lee, C. L. Lin, K. P. Huang, K. M. Chen, Y. Li, S. Samukawa, T. S. Chao, G. W. Huang, W. F. Wu, W. H. Lee, J. Y. Li, J. M. Shieh, J. H. Tarng, Y. H. Wang, W. K. Yeh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

In this work, we demonstrate vertically stacked heterogeneous dual-workfunction gate complementary FET (CFET) inverters and 6T-SRAM with n-Type IGZO and p-Type polysilicon channels for the first time. The dual-workfunction gate structure with adjusted gate biasing allows the adjustment of channel potential to match the threshold voltage of transistors for CMOS and SRAM operation. High-frequency IGZO RF devices with p-Type silicon isolation are fabricated simultaneously with the same process. Novel etching process based on fluorine-based gas with an extremely high-etching selectivity between the source/drain metal and the IGZO facilitates the definition of the source/drain region. IGZO surface treated with fluorine-based gas during over-etching step allows a low leakage current shallow passivation layer to optimize direct current characteristics.

Original language	English
Title of host publication	2021 IEEE International Electron Devices Meeting, IEDM 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	34.4.1-34.4.4
ISBN (Electronic)	9781665425728
DOIs	https://doi.org/10.1109/IEDM19574.2021.9720675
Publication status	Published - 2021
Event	2021 IEEE International Electron Devices Meeting, IEDM 2021 - San Francisco, United States Duration: 2021 Dec 11 → 2021 Dec 16

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2021-December
ISSN (Print)	0163-1918

Conference

Conference	2021 IEEE International Electron Devices Meeting, IEDM 2021
Country/Territory	United States
City	San Francisco
Period	21-12-11 → 21-12-16

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Materials Chemistry
Electrical and Electronic Engineering

Access to Document

10.1109/IEDM19574.2021.9720675

Cite this

Chang, S. W., Lu, T. H., Yang, C. Y., Yeh, C. J., Huang, M. K., Meng, C. F., Chen, P. J., Chang, T. H., Chang, Y. S., Jhu, J. W., Hong, T. Z., Ke, C. C., Yu, X. R., Lu, W. H., Baig, M. A., Cho, T. C., Sung, P. J., Su, C. J., Hsueh, F. K., ... Yeh, W. K. (2021). First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications. In 2021 IEEE International Electron Devices Meeting, IEDM 2021 (pp. 34.4.1-34.4.4). (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2021-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM19574.2021.9720675

Chang, S. W. ; Lu, T. H. ; Yang, C. Y. et al. / First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications. 2021 IEEE International Electron Devices Meeting, IEDM 2021. Institute of Electrical and Electronics Engineers Inc., 2021. pp. 34.4.1-34.4.4 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{6c9a2130a9084717be3c404405b229ea,

title = "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications",

abstract = "In this work, we demonstrate vertically stacked heterogeneous dual-workfunction gate complementary FET (CFET) inverters and 6T-SRAM with n-Type IGZO and p-Type polysilicon channels for the first time. The dual-workfunction gate structure with adjusted gate biasing allows the adjustment of channel potential to match the threshold voltage of transistors for CMOS and SRAM operation. High-frequency IGZO RF devices with p-Type silicon isolation are fabricated simultaneously with the same process. Novel etching process based on fluorine-based gas with an extremely high-etching selectivity between the source/drain metal and the IGZO facilitates the definition of the source/drain region. IGZO surface treated with fluorine-based gas during over-etching step allows a low leakage current shallow passivation layer to optimize direct current characteristics.",

author = "Chang, {S. W.} and Lu, {T. H.} and Yang, {C. Y.} and Yeh, {C. J.} and Huang, {M. K.} and Meng, {C. F.} and Chen, {P. J.} and Chang, {T. H.} and Chang, {Y. S.} and Jhu, {J. W.} and Hong, {T. Z.} and Ke, {C. C.} and Yu, {X. R.} and Lu, {W. H.} and Baig, {M. A.} and Cho, {T. C.} and Sung, {P. J.} and Su, {C. J.} and Hsueh, {F. K.} and Chen, {B. Y.} and Hu, {H. H.} and Wu, {C. T.} and Lin, {K. L.} and Ma, {W. C.Y.} and Lu, {D. D.} and Kao, {K. H.} and Lee, {Y. J.} and Lin, {C. L.} and Huang, {K. P.} and Chen, {K. M.} and Y. Li and S. Samukawa and Chao, {T. S.} and Huang, {G. W.} and Wu, {W. F.} and Lee, {W. H.} and Li, {J. Y.} and Shieh, {J. M.} and Tarng, {J. H.} and Wang, {Y. H.} and Yeh, {W. K.}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 IEEE International Electron Devices Meeting, IEDM 2021 ; Conference date: 11-12-2021 Through 16-12-2021",

year = "2021",

doi = "10.1109/IEDM19574.2021.9720675",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "34.4.1--34.4.4",

booktitle = "2021 IEEE International Electron Devices Meeting, IEDM 2021",

address = "United States",

}

Chang, SW, Lu, TH, Yang, CY, Yeh, CJ, Huang, MK, Meng, CF, Chen, PJ, Chang, TH, Chang, YS, Jhu, JW, Hong, TZ, Ke, CC, Yu, XR, Lu, WH, Baig, MA, Cho, TC, Sung, PJ, Su, CJ, Hsueh, FK, Chen, BY, Hu, HH, Wu, CT, Lin, KL, Ma, WCY, Lu, DD , Kao, KH, Lee, YJ, Lin, CL, Huang, KP, Chen, KM, Li, Y, Samukawa, S, Chao, TS, Huang, GW, Wu, WF, Lee, WH, Li, JY, Shieh, JM, Tarng, JH, Wang, YH & Yeh, WK 2021, First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications. in 2021 IEEE International Electron Devices Meeting, IEDM 2021. Technical Digest - International Electron Devices Meeting, IEDM, vol. 2021-December, Institute of Electrical and Electronics Engineers Inc., pp. 34.4.1-34.4.4, 2021 IEEE International Electron Devices Meeting, IEDM 2021, San Francisco, United States, 21-12-11. https://doi.org/10.1109/IEDM19574.2021.9720675

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications. / Chang, S. W.; Lu, T. H.; Yang, C. Y. et al.
2021 IEEE International Electron Devices Meeting, IEDM 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 34.4.1-34.4.4 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2021-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications

AU - Chang, S. W.

AU - Lu, T. H.

AU - Yang, C. Y.

AU - Yeh, C. J.

AU - Huang, M. K.

AU - Meng, C. F.

AU - Chen, P. J.

AU - Chang, T. H.

AU - Chang, Y. S.

AU - Jhu, J. W.

AU - Hong, T. Z.

AU - Ke, C. C.

AU - Yu, X. R.

AU - Lu, W. H.

AU - Baig, M. A.

AU - Cho, T. C.

AU - Sung, P. J.

AU - Su, C. J.

AU - Hsueh, F. K.

AU - Chen, B. Y.

AU - Hu, H. H.

AU - Wu, C. T.

AU - Lin, K. L.

AU - Ma, W. C.Y.

AU - Lu, D. D.

AU - Kao, K. H.

AU - Lee, Y. J.

AU - Lin, C. L.

AU - Huang, K. P.

AU - Chen, K. M.

AU - Li, Y.

AU - Samukawa, S.

AU - Chao, T. S.

AU - Huang, G. W.

AU - Wu, W. F.

AU - Lee, W. H.

AU - Li, J. Y.

AU - Shieh, J. M.

AU - Tarng, J. H.

AU - Wang, Y. H.

AU - Yeh, W. K.

PY - 2021

Y1 - 2021

N2 - In this work, we demonstrate vertically stacked heterogeneous dual-workfunction gate complementary FET (CFET) inverters and 6T-SRAM with n-Type IGZO and p-Type polysilicon channels for the first time. The dual-workfunction gate structure with adjusted gate biasing allows the adjustment of channel potential to match the threshold voltage of transistors for CMOS and SRAM operation. High-frequency IGZO RF devices with p-Type silicon isolation are fabricated simultaneously with the same process. Novel etching process based on fluorine-based gas with an extremely high-etching selectivity between the source/drain metal and the IGZO facilitates the definition of the source/drain region. IGZO surface treated with fluorine-based gas during over-etching step allows a low leakage current shallow passivation layer to optimize direct current characteristics.

AB - In this work, we demonstrate vertically stacked heterogeneous dual-workfunction gate complementary FET (CFET) inverters and 6T-SRAM with n-Type IGZO and p-Type polysilicon channels for the first time. The dual-workfunction gate structure with adjusted gate biasing allows the adjustment of channel potential to match the threshold voltage of transistors for CMOS and SRAM operation. High-frequency IGZO RF devices with p-Type silicon isolation are fabricated simultaneously with the same process. Novel etching process based on fluorine-based gas with an extremely high-etching selectivity between the source/drain metal and the IGZO facilitates the definition of the source/drain region. IGZO surface treated with fluorine-based gas during over-etching step allows a low leakage current shallow passivation layer to optimize direct current characteristics.

UR - http://www.scopus.com/inward/record.url?scp=85127000636&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85127000636&partnerID=8YFLogxK

U2 - 10.1109/IEDM19574.2021.9720675

DO - 10.1109/IEDM19574.2021.9720675

M3 - Conference contribution

AN - SCOPUS:85127000636

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 34.4.1-34.4.4

BT - 2021 IEEE International Electron Devices Meeting, IEDM 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2021 IEEE International Electron Devices Meeting, IEDM 2021

Y2 - 11 December 2021 through 16 December 2021

ER -

Chang SW, Lu TH, Yang CY, Yeh CJ, Huang MK, Meng CF et al. First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications. In 2021 IEEE International Electron Devices Meeting, IEDM 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 34.4.1-34.4.4. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM19574.2021.9720675

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications

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