This study proposes and demonstrates a novel heterogeneous L-shaped FET (LFET) structure consisting of a vertical epitaxially-grown Ge pFET above a lateral Si nFET for the first time. The fabrication challenges of the heterogeneous CFET structure, consisting of a lateral Ge pFET and a lateral Si nFET, are greatly alleviated with the new LFET design. Despite comparable layout footprint for logic and SRAM cells, LFET outperforms CFET with lower parasitic resistances and capacitances for the p-channel device, both leading to reduced gate delay, particularly for the low-to-high logic transition, according to TCAD simulations. LFET exhibits 32.5% lower power for the same operating frequency, or 35% frequency gain for the same operating power. Heterogenous LFET devices with junctionless channels and high- kappa and metal gate stacks are successfully fabricated on SOI substrate, with operational n-channel, p-channel devices, and CMOS inverters.