First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT)

T. Z. Hong; W. H. Chang; A. Agarwal; Y. T. Huang; C. Y. Yang; T. Y. Chu; H. Y. Chao; Y. Chuang; S. T. Chung; J. H. Lin; S. M. Luo; C. J. Tsai; M. J. Li; X. R. Yu; N. C. Lin; T. C. Cho; P. J. Sung; C. J. Su; G. L. Luo; F. K. Hsueh; K. L. Lin; H. Ishii; T. Irisawa; T. Maeda; C. T. Wu; W. C.Y. Ma; D. D. Lu; K. H. Kao; Y. J. Lee; H. J.H. Chen; C. L. Lin; R. W. Chuang; K. P. Huang; S. Samukawa; Y. M. Li; J. H. Tarng; T. S. Chao; M. Miura; G. W. Huang; W. F. Wu; J. Y. Li; J. M. Shieh; Y. H. Wang; W. K. Yeh

doi:10.1109/IEDM13553.2020.9372001

First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT)

T. Z. Hong, W. H. Chang, A. Agarwal, Y. T. Huang, C. Y. Yang, T. Y. Chu, H. Y. Chao, Y. Chuang, S. T. Chung, J. H. Lin, S. M. Luo, C. J. Tsai, M. J. Li, X. R. Yu, N. C. Lin, T. C. Cho, P. J. Sung, C. J. Su, G. L. Luo, F. K. HsuehK. L. Lin, H. Ishii, T. Irisawa, T. Maeda, C. T. Wu, W. C.Y. Ma, D. D. Lu, K. H. Kao, Y. J. Lee, H. J.H. Chen, C. L. Lin, R. W. Chuang, K. P. Huang, S. Samukawa, Y. M. Li, J. H. Tarng, T. S. Chao, M. Miura, G. W. Huang, W. F. Wu, J. Y. Li, J. M. Shieh, Y. H. Wang, W. K. Yeh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.

Original language	English
Title of host publication	2020 IEEE International Electron Devices Meeting, IEDM 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	15.5.1-15.5.4
ISBN (Electronic)	9781728188881
DOIs	https://doi.org/10.1109/IEDM13553.2020.9372001
Publication status	Published - 2020 Dec 12
Event	66th Annual IEEE International Electron Devices Meeting, IEDM 2020 - Virtual, San Francisco, United States Duration: 2020 Dec 12 → 2020 Dec 18

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2020-December
ISSN (Print)	0163-1918

Conference

Conference	66th Annual IEEE International Electron Devices Meeting, IEDM 2020
Country/Territory	United States
City	Virtual, San Francisco
Period	20-12-12 → 20-12-18

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM13553.2020.9372001

Cite this

Hong, T. Z., Chang, W. H., Agarwal, A., Huang, Y. T., Yang, C. Y., Chu, T. Y., Chao, H. Y., Chuang, Y., Chung, S. T., Lin, J. H., Luo, S. M., Tsai, C. J., Li, M. J., Yu, X. R., Lin, N. C., Cho, T. C., Sung, P. J., Su, C. J., Luo, G. L., ... Yeh, W. K. (2020). First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT). In 2020 IEEE International Electron Devices Meeting, IEDM 2020 (pp. 15.5.1-15.5.4). Article 9372001 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2020-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM13553.2020.9372001

Hong, T. Z. ; Chang, W. H. ; Agarwal, A. et al. / First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT). 2020 IEEE International Electron Devices Meeting, IEDM 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 15.5.1-15.5.4 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{288cc1a5eec849388380e34daabf384c,

title = "First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT)",

abstract = "For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.",

author = "Hong, {T. Z.} and Chang, {W. H.} and A. Agarwal and Huang, {Y. T.} and Yang, {C. Y.} and Chu, {T. Y.} and Chao, {H. Y.} and Y. Chuang and Chung, {S. T.} and Lin, {J. H.} and Luo, {S. M.} and Tsai, {C. J.} and Li, {M. J.} and Yu, {X. R.} and Lin, {N. C.} and Cho, {T. C.} and Sung, {P. J.} and Su, {C. J.} and Luo, {G. L.} and Hsueh, {F. K.} and Lin, {K. L.} and H. Ishii and T. Irisawa and T. Maeda and Wu, {C. T.} and Ma, {W. C.Y.} and Lu, {D. D.} and Kao, {K. H.} and Lee, {Y. J.} and Chen, {H. J.H.} and Lin, {C. L.} and Chuang, {R. W.} and Huang, {K. P.} and S. Samukawa and Li, {Y. M.} and Tarng, {J. H.} and Chao, {T. S.} and M. Miura and Huang, {G. W.} and Wu, {W. F.} and Li, {J. Y.} and Shieh, {J. M.} and Wang, {Y. H.} and Yeh, {W. K.}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 66th Annual IEEE International Electron Devices Meeting, IEDM 2020 ; Conference date: 12-12-2020 Through 18-12-2020",

year = "2020",

month = dec,

day = "12",

doi = "10.1109/IEDM13553.2020.9372001",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "15.5.1--15.5.4",

booktitle = "2020 IEEE International Electron Devices Meeting, IEDM 2020",

address = "United States",

}

Hong, TZ, Chang, WH, Agarwal, A, Huang, YT, Yang, CY, Chu, TY, Chao, HY, Chuang, Y, Chung, ST, Lin, JH, Luo, SM, Tsai, CJ, Li, MJ, Yu, XR, Lin, NC, Cho, TC, Sung, PJ, Su, CJ, Luo, GL, Hsueh, FK, Lin, KL, Ishii, H, Irisawa, T, Maeda, T, Wu, CT, Ma, WCY, Lu, DD , Kao, KH, Lee, YJ, Chen, HJH, Lin, CL, Chuang, RW, Huang, KP, Samukawa, S, Li, YM, Tarng, JH, Chao, TS, Miura, M, Huang, GW, Wu, WF, Li, JY, Shieh, JM, Wang, YH & Yeh, WK 2020, First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT). in 2020 IEEE International Electron Devices Meeting, IEDM 2020., 9372001, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2020-December, Institute of Electrical and Electronics Engineers Inc., pp. 15.5.1-15.5.4, 66th Annual IEEE International Electron Devices Meeting, IEDM 2020, Virtual, San Francisco, United States, 20-12-12. https://doi.org/10.1109/IEDM13553.2020.9372001

First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT). / Hong, T. Z.; Chang, W. H.; Agarwal, A. et al.
2020 IEEE International Electron Devices Meeting, IEDM 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 15.5.1-15.5.4 9372001 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2020-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT)

AU - Hong, T. Z.

AU - Chang, W. H.

AU - Agarwal, A.

AU - Huang, Y. T.

AU - Yang, C. Y.

AU - Chu, T. Y.

AU - Chao, H. Y.

AU - Chuang, Y.

AU - Chung, S. T.

AU - Lin, J. H.

AU - Luo, S. M.

AU - Tsai, C. J.

AU - Li, M. J.

AU - Yu, X. R.

AU - Lin, N. C.

AU - Cho, T. C.

AU - Sung, P. J.

AU - Su, C. J.

AU - Luo, G. L.

AU - Hsueh, F. K.

AU - Lin, K. L.

AU - Ishii, H.

AU - Irisawa, T.

AU - Maeda, T.

AU - Wu, C. T.

AU - Ma, W. C.Y.

AU - Lu, D. D.

AU - Kao, K. H.

AU - Lee, Y. J.

AU - Chen, H. J.H.

AU - Lin, C. L.

AU - Chuang, R. W.

AU - Huang, K. P.

AU - Samukawa, S.

AU - Li, Y. M.

AU - Tarng, J. H.

AU - Chao, T. S.

AU - Miura, M.

AU - Huang, G. W.

AU - Wu, W. F.

AU - Li, J. Y.

AU - Shieh, J. M.

AU - Wang, Y. H.

AU - Yeh, W. K.

PY - 2020/12/12

Y1 - 2020/12/12

N2 - For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.

AB - For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.

UR - http://www.scopus.com/inward/record.url?scp=85102917891&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85102917891&partnerID=8YFLogxK

U2 - 10.1109/IEDM13553.2020.9372001

DO - 10.1109/IEDM13553.2020.9372001

M3 - Conference contribution

AN - SCOPUS:85102917891

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 15.5.1-15.5.4

BT - 2020 IEEE International Electron Devices Meeting, IEDM 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 66th Annual IEEE International Electron Devices Meeting, IEDM 2020

Y2 - 12 December 2020 through 18 December 2020

ER -

Hong TZ, Chang WH, Agarwal A, Huang YT, Yang CY, Chu TY et al. First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT). In 2020 IEEE International Electron Devices Meeting, IEDM 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 15.5.1-15.5.4. 9372001. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM13553.2020.9372001

First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT)

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