Flash memory die sort by a sample classification method

Yu Chun Dawn, Jen Chieh Yeh, Cheng Wen Wu, Chia Ching Wang, Yung Chen Lin, Chao Hsun Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution


As the memory cells keep scaling down and designs are getting bigger and faster, uncertainty is becoming one of the greatest challenges for the semiconductor industry. Unexpected and unpredictable behaviors of devices usually lead to poor quality and reliability. Low-cost test techniques that improves die sorting accuracy thus are critical for advanced devices. Flash memory is more prone to such problem compared with others. Large capacity, high density, and complicated cell structure makes flash memory cell behavior difficult to predict precisely. Even when we test the dies on the same wafer it can be bothering, as each of them may ask for different test condition due to geometric process variation. As a fast and easy-to-use method to solve the problem, we propose a sample classification method. It is not only effective for flash memory testing, but also for other types of circuits that face similar test problem. Experimental result shows that the method solves the flash memory die sort problem efficiently and accurately. The test time is greatly reduced - for an industrial chip, the test time is reduced from 8,817 ms to 718 ms. Moreover, the proposed approach is also suitable for design-for-testability (DFT) implementation that can easily be integrated with a commodity or embedded memory.

Original languageEnglish
Title of host publicationProceedings - 14th Asian Test Symposium, ATS 2005
Number of pages6
Publication statusPublished - 2005 Dec 1
Event14th Asian Test Symposium, ATS 2005 - Calcutta, India
Duration: 2005 Dec 182005 Dec 21

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference14th Asian Test Symposium, ATS 2005

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Hardware and Architecture


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