Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors

Hong Chih Chen, Yu Ching Tsao, An Kuo Chu, Hui Chun Huang, Wei Chih Lai, Guan Fu Chen, Shin Ping Huang, Ting Chang Chang, Po Hsun Chen, Jian Jie Chen, Chuan Wei Kuo, Kuan Ju Zhou, Yang Hao Hung

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Abstract

This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field.

Original languageEnglish
Article number8880614
Pages (from-to)1941-1944
Number of pages4
JournalIEEE Electron Device Letters
Volume40
Issue number12
DOIs
Publication statusPublished - 2019 Dec

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Chen, H. C., Tsao, Y. C., Chu, A. K., Huang, H. C., Lai, W. C., Chen, G. F., Huang, S. P., Chang, T. C., Chen, P. H., Chen, J. J., Kuo, C. W., Zhou, K. J., & Hung, Y. H. (2019). Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors. IEEE Electron Device Letters, 40(12), 1941-1944. [8880614]. https://doi.org/10.1109/LED.2019.2949243