FPGA-based hardware emulator for fast fault emulation

Jin Hua Hong, Shih Arn Hwang, Cheng Wen Wu

Research output: Contribution to conferencePaperpeer-review

4 Citations (Scopus)


An FPGA-based hardware emulation system is shown to boost the speed of fault simulation for sequential circuits. The circuit downloaded into the emulation system which emulates the faulty circuit's behavior is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection chain, with which we get rid of the highly time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that the fault emulator is about twenty times faster than HOPE (a parallel fault simulator). A parallel fault emulation approach is also proposed, in which faults that are not activated or with short propagation distance are screened off before fault emulation, and non-stem faults are collapsed into their equivalent stem faults, further reducing the number of faults actually emulated.

Original languageEnglish
Number of pages4
Publication statusPublished - 1996 Dec 1
EventProceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3) - Ames, IA, USA
Duration: 1996 Aug 181996 Aug 21


OtherProceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3)
CityAmes, IA, USA

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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