TY - GEN
T1 - FPGA realization of line-interactive uninterruptible power supply
AU - Huang, Shyh-Jier
AU - Sun, Chia Hung
AU - Lee, Tsong Shing
PY - 2003/1/1
Y1 - 2003/1/1
N2 - A novel design of line-interactive uninterruptible power supplies is proposed in this paper. In the designated circuit, by utilizing single-stage power converter, the system can be operated either in the active power filter mode or in the voltage-stabilizing mode based on the operating state of mains power. When the system is operated at the active power filter mode, both the harmonic reduction and reactive power compensation can be achieved via a set of current feedback signals. When the system is operated at the voltage-stabilizing mode, by deeming the capacitor current as the control variable, the first-order current control method can be formulated such that the system stability is maintained while the speed response is significantly improved, With the aid of the FPGA in the digital design, it is found that the hardware circuit can be realized within a shorter time and the design cost can be also lowered down. This proposed system has been validated by theoretical analysis and experimental realization. Test results support the feasibility of the proposed approach for the application considered.
AB - A novel design of line-interactive uninterruptible power supplies is proposed in this paper. In the designated circuit, by utilizing single-stage power converter, the system can be operated either in the active power filter mode or in the voltage-stabilizing mode based on the operating state of mains power. When the system is operated at the active power filter mode, both the harmonic reduction and reactive power compensation can be achieved via a set of current feedback signals. When the system is operated at the voltage-stabilizing mode, by deeming the capacitor current as the control variable, the first-order current control method can be formulated such that the system stability is maintained while the speed response is significantly improved, With the aid of the FPGA in the digital design, it is found that the hardware circuit can be realized within a shorter time and the design cost can be also lowered down. This proposed system has been validated by theoretical analysis and experimental realization. Test results support the feasibility of the proposed approach for the application considered.
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U2 - 10.1109/PEDS.2003.1282857
DO - 10.1109/PEDS.2003.1282857
M3 - Conference contribution
AN - SCOPUS:84961616015
T3 - Proceedings of the International Conference on Power Electronics and Drive Systems
SP - 376
EP - 379
BT - 5th International Conference on Power Electronics and Drive Systems, PEDS 2003 - Proceedings
A2 - Tseng, King-Jet
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th International Conference on Power Electronics and Drive Systems, PEDS 2003
Y2 - 17 November 2003 through 20 November 2003
ER -