Full system simulation and verification framework

Jing Wun Lin, Chen Chieh Wang, Chin Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan Hua Chu, Jen Chieh Yeh, Ying Chuan Hsiao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

In this paper, we propose a framework to develop high-performance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.

Original languageEnglish
Title of host publication5th International Conference on Information Assurance and Security, IAS 2009
Pages165-168
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event5th International Conference on Information Assurance and Security, IAS 2009 - Xian, China
Duration: 2009 Aug 182009 Sep 20

Publication series

Name5th International Conference on Information Assurance and Security, IAS 2009
Volume1

Other

Other5th International Conference on Information Assurance and Security, IAS 2009
CountryChina
CityXian
Period09-08-1809-09-20

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Computer Science Applications
  • Hardware and Architecture
  • Software

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  • Cite this

    Lin, J. W., Wang, C. C., Chang, C. Y., Chen, C-H., Lee, K-J., Chu, Y. H., Yeh, J. C., & Hsiao, Y. C. (2009). Full system simulation and verification framework. In 5th International Conference on Information Assurance and Security, IAS 2009 (pp. 165-168). [5283808] (5th International Conference on Information Assurance and Security, IAS 2009; Vol. 1). https://doi.org/10.1109/IAS.2009.253