TY - GEN
T1 - Full system simulation and verification framework
AU - Lin, Jing Wun
AU - Wang, Chen Chieh
AU - Chang, Chin Yao
AU - Chen, Chung-Ho
AU - Lee, Kuen-Jong
AU - Chu, Yuan Hua
AU - Yeh, Jen Chieh
AU - Hsiao, Ying Chuan
PY - 2009/12/1
Y1 - 2009/12/1
N2 - In this paper, we propose a framework to develop high-performance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.
AB - In this paper, we propose a framework to develop high-performance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.
UR - http://www.scopus.com/inward/record.url?scp=74049142335&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=74049142335&partnerID=8YFLogxK
U2 - 10.1109/IAS.2009.253
DO - 10.1109/IAS.2009.253
M3 - Conference contribution
AN - SCOPUS:74049142335
SN - 9780769537443
T3 - 5th International Conference on Information Assurance and Security, IAS 2009
SP - 165
EP - 168
BT - 5th International Conference on Information Assurance and Security, IAS 2009
T2 - 5th International Conference on Information Assurance and Security, IAS 2009
Y2 - 18 August 2009 through 20 September 2009
ER -