Functional test pattern generation for asynchronous circuits

Jar Shone Ker, Yau-Hwang Kuo, Bin-Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Various approaches for functional test generation have been discussed and proposed in the past decade. The most significant difference lies in the circuit modeling methodologies, such as BDD, RTLs, HDLs, state transition diagram. In this paper, we develop a functional test generation algorithm, which generates test patterns directly from a graphical model, called the signal transition graph (STG). STG has been widely used for the design and modeling of asynchronous circuits, so we focus on the test generation for asynchronous circuits. In addition, we propose a token propagation fault model to model the fault effects exhibiting on STG, and apply the equivalence/dominance fault collapsing analysis to reduce the number of faults to be considered.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1519-1522
Number of pages4
ISBN (Print)0780312813
Publication statusPublished - 1993 Jan 1
EventProceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
Duration: 1993 May 31993 May 6

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Other

OtherProceedings of the 1993 IEEE International Symposium on Circuits and Systems
CityChicago, IL, USA
Period93-05-0393-05-06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Ker, J. S., Kuo, Y-H., & Liu, B-D. (1993). Functional test pattern generation for asynchronous circuits. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1519-1522). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3). Publ by IEEE.