Functional verifications for SoC software/hardware co-design: From virtual platform to physical platform

Yi Li Lin, Alvin W.Y. Su

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper applies heterogeneous simulation to achieve system and functional level co-verification throughout SoC design flow. It reduces high verification complexity resulted from covering software and hardware works and involving various tools. Stubs for data transport and a Verification Router for heterogeneous simulation management are proposed. A functional module is transformed from a highly abstract model to its target design progressively through a series of intermediate models. Those models can be validated as a portion of a complete SoC system model. The proposed heterogeneous verification is demonstrated with a jpeg encoder.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2011
Pages201-206
Number of pages6
DOIs
Publication statusPublished - 2011 Dec 28
Event24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan
Duration: 2011 Sep 262011 Sep 28

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Other

Other24th IEEE International System on Chip Conference, SOCC 2011
CountryTaiwan
CityTaipei
Period11-09-2611-09-28

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Lin, Y. L., & Su, A. W. Y. (2011). Functional verifications for SoC software/hardware co-design: From virtual platform to physical platform. In Proceedings - IEEE International SOC Conference, SOCC 2011 (pp. 201-206). [6085104] (International System on Chip Conference). https://doi.org/10.1109/SOCC.2011.6085104