TY - GEN
T1 - Functional verifications for SoC software/hardware co-design
T2 - 24th IEEE International System on Chip Conference, SOCC 2011
AU - Lin, Yi Li
AU - Su, Alvin W.Y.
PY - 2011/12/28
Y1 - 2011/12/28
N2 - This paper applies heterogeneous simulation to achieve system and functional level co-verification throughout SoC design flow. It reduces high verification complexity resulted from covering software and hardware works and involving various tools. Stubs for data transport and a Verification Router for heterogeneous simulation management are proposed. A functional module is transformed from a highly abstract model to its target design progressively through a series of intermediate models. Those models can be validated as a portion of a complete SoC system model. The proposed heterogeneous verification is demonstrated with a jpeg encoder.
AB - This paper applies heterogeneous simulation to achieve system and functional level co-verification throughout SoC design flow. It reduces high verification complexity resulted from covering software and hardware works and involving various tools. Stubs for data transport and a Verification Router for heterogeneous simulation management are proposed. A functional module is transformed from a highly abstract model to its target design progressively through a series of intermediate models. Those models can be validated as a portion of a complete SoC system model. The proposed heterogeneous verification is demonstrated with a jpeg encoder.
UR - http://www.scopus.com/inward/record.url?scp=84255188944&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84255188944&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2011.6085104
DO - 10.1109/SOCC.2011.6085104
M3 - Conference contribution
AN - SCOPUS:84255188944
SN - 9781457716164
T3 - International System on Chip Conference
SP - 201
EP - 206
BT - Proceedings - IEEE International SOC Conference, SOCC 2011
Y2 - 26 September 2011 through 28 September 2011
ER -