GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

Ya Chi Huang, Meng Hsueh Chiang, Shui Jinn Wang, Jerry G. Fossum

Research output: Contribution to journalArticlepeer-review

28 Citations (Scopus)


Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.

Original languageEnglish
Article number7890390
Pages (from-to)164-169
Number of pages6
JournalIEEE Journal of the Electron Devices Society
Issue number3
Publication statusPublished - 2017 May

All Science Journal Classification (ASJC) codes

  • Biotechnology
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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