GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

Ya Chi Huang; Meng Hsueh Chiang; Shui Jinn Wang; Jerry G. Fossum

doi:10.1109/JEDS.2017.2689738

GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

Ya Chi Huang
, Meng Hsueh Chiang
, Shui Jinn Wang
, Jerry G. Fossum

Research output: Contribution to journal › Article › peer-review

86 Citations (Scopus)

Abstract

Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.

Original language	English
Article number	7890390
Pages (from-to)	164-169
Number of pages	6
Journal	IEEE Journal of the Electron Devices Society
Volume	5
Issue number	3
DOIs	https://doi.org/10.1109/JEDS.2017.2689738
Publication status	Published - 2017 May

All Science Journal Classification (ASJC) codes

Biotechnology
Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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abstract = "Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.",

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GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

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