Generalization of an enhanced ECC methodology for low power PSRAM

Po Yuan Chen, Chin Lung Su, Chao Hsun Chen, Cheng Wen Wu

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)

Abstract

Error control codes (ECCs) have been widely used to maintain the reliability of memories, but ordinary ECC codes are not suitable for memories with long codewords. For portable products, power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve these issues, we have proposed a parallel encoding and decoding ECC scheme to reduce refresh power for an industrial pseudo-SRAM (PSRAM) with long codewords. In this paper, we briefly review the scheme and propose a systematic way to generate the parity check matrix for the new ECC scheme. We also modify the parity correction mechanism to reduce the operating power of the scheme. As for the 70 ns access time of the 256-MB PSRAM with 64-bit codewords and 16-bit I/O, experimental results show that the new ECC scheme can be integrated with the READ/WRITE operations with about 0.2 percent circuit area overhead and less than 3.5 ns encoding/decoding time. The new ECC architecture provides a flexible solution for memories with different widths of ECC codewords and I/O ports, without the error masking effect or reduction in reliability.

Original languageEnglish
Article number6189334
Pages (from-to)1318-1331
Number of pages14
JournalIEEE Transactions on Computers
Volume62
Issue number7
DOIs
Publication statusPublished - 2013 Jun 5

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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