Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run

Yi Cheng Kung, Kuen Jong Lee, Sudhakar M. Reddy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS'89, IWLS'05 and ITC'99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55%, 11.26% and 13.69% and reduce test application time by 25.93%, 24.47% and 31.67%, respectively, without degrading fault coverage.

Original languageEnglish
Title of host publicationInternational Test Conference 2018, ITC 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538683828
DOIs
Publication statusPublished - 2019 Jan 23
Event49th IEEE International Test Conference, ITC 2018 - Phoenix, United States
Duration: 2018 Oct 292018 Nov 1

Publication series

NameProceedings - International Test Conference
Volume2018-October
ISSN (Print)1089-3539

Conference

Conference49th IEEE International Test Conference, ITC 2018
CountryUnited States
CityPhoenix
Period18-10-2918-11-01

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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