Abstract
A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS'89, IWLS'05 and ITC'99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55%, 11.26% and 13.69% and reduce test application time by 25.93%, 24.47% and 31.67%, respectively, without degrading fault coverage.
| Original language | English |
|---|---|
| Title of host publication | International Test Conference 2018, ITC 2018 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781538683828 |
| DOIs | |
| Publication status | Published - 2019 Jan 23 |
| Event | 49th IEEE International Test Conference, ITC 2018 - Phoenix, United States Duration: 2018 Oct 29 → 2018 Nov 1 |
Publication series
| Name | Proceedings - International Test Conference |
|---|---|
| Volume | 2018-October |
| ISSN (Print) | 1089-3539 |
Conference
| Conference | 49th IEEE International Test Conference, ITC 2018 |
|---|---|
| Country | United States |
| City | Phoenix |
| Period | 18-10-29 → 18-11-01 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Applied Mathematics
Cite this
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Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. / Kung, Yi Cheng; Lee, Kuen Jong; Reddy, Sudhakar M.
International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8624678 (Proceedings - International Test Conference; Vol. 2018-October).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run
AU - Kung, Yi Cheng
AU - Lee, Kuen Jong
AU - Reddy, Sudhakar M.
PY - 2019/1/23
Y1 - 2019/1/23
N2 - A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS'89, IWLS'05 and ITC'99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55%, 11.26% and 13.69% and reduce test application time by 25.93%, 24.47% and 31.67%, respectively, without degrading fault coverage.
AB - A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS'89, IWLS'05 and ITC'99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55%, 11.26% and 13.69% and reduce test application time by 25.93%, 24.47% and 31.67%, respectively, without degrading fault coverage.
UR - http://www.scopus.com/inward/record.url?scp=85062394477&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85062394477&partnerID=8YFLogxK
U2 - 10.1109/TEST.2018.8624678
DO - 10.1109/TEST.2018.8624678
M3 - Conference contribution
AN - SCOPUS:85062394477
T3 - Proceedings - International Test Conference
BT - International Test Conference 2018, ITC 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -