Generating compact test patterns for stuck-at faults and transition faults in one ATPG run

Yi Cheng Kung, Kuen Jong Lee, Sudhakar M. Reddy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper presents a novel test pattern generation flow to detect stuck-at and transition faults simultaneously. Both fault models are transformed into a unified fault model for a proposed 2-time-frame circuit model. This makes it possible to generate patterns for both types of faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set can thus be obtained which requires less test data volume and shorter test application time without degrading the fault coverage for either type of faults. Experimental results show that, compared to the conventional methods, the proposed method can reduce the total test pattern counts by up to 12.27% and 15.54% and test application times up to 12.06% and 15.58% for ISCAS'89 and ITC'99 circuits, respectively.

Original languageEnglish
Title of host publicationProceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-6
Number of pages6
ISBN (Print)9781538651803
DOIs
Publication statusPublished - 2018 Sep 11
Event2nd IEEE International Test Conference in Asia, ITC-Asia 2018 - Harbin, China
Duration: 2018 Aug 152018 Aug 17

Publication series

NameProceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018

Other

Other2nd IEEE International Test Conference in Asia, ITC-Asia 2018
CountryChina
CityHarbin
Period18-08-1518-08-17

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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