Generating Single-and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

Yi Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy

Research output: Contribution to journalArticle

Abstract

A novel test pattern generation method for multiple DC and AC faults is presented. The fault models considered include line stuck-at, bridging, transition and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both DC and AC faults in one ATPG run without needing to modify the ATPG tool. Both LOC and LOS test methods are supported. Experimental results on ISCAS’89 and ITC’99 benchmark circuits show the effectiveness of the proposed method compared to earlier proposed methods.

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Networks (circuits)
Transistors

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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title = "Generating Single-and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run",
abstract = "A novel test pattern generation method for multiple DC and AC faults is presented. The fault models considered include line stuck-at, bridging, transition and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both DC and AC faults in one ATPG run without needing to modify the ATPG tool. Both LOC and LOS test methods are supported. Experimental results on ISCAS’89 and ITC’99 benchmark circuits show the effectiveness of the proposed method compared to earlier proposed methods.",
author = "Kung, {Yi Cheng} and Kuen-Jong Lee and Reddy, {Sudhakar M.}",
year = "2019",
month = "1",
day = "1",
doi = "10.1109/TCAD.2019.2921345",
language = "English",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

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AB - A novel test pattern generation method for multiple DC and AC faults is presented. The fault models considered include line stuck-at, bridging, transition and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both DC and AC faults in one ATPG run without needing to modify the ATPG tool. Both LOC and LOS test methods are supported. Experimental results on ISCAS’89 and ITC’99 benchmark circuits show the effectiveness of the proposed method compared to earlier proposed methods.

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