The etching rate in silicon deep reactive ion etching (RIE) is related to pattern geometry and a frequently seen defect, RIE lag, appears in feature sizes up to hundreds of micrometers. Different feature dimensions of rectangles, squares and circles/doughnuts are designed to realize how the geometrical pattern affects RIE lag in the inductively coupled plasma (ICP) etching process. Experimental results reveal that the primary dominating factor in RIE lag is feature width and secondary factors are feature area, shape and length-to-width ratio. Etching rates of rectangular trenches are sensitive to width while ring trenches are sensitive to both width and area. Process parameters are also adjusted to control RIE lag magnitude and realize its mechanism. The inverse RIE lag phenomenon appears at a much higher pressure of APC (auto pressure control) 75% at constant area features. The formation and removal of passivation film at the trench bottom will delay Si etching by F radical density, which will start earlier in a small width than a large one. It will be more obvious at higher pressure and lead to the reduction of RIE lag. This indicates that the cause of RIE lag in ICP etching is primarily attributed to the formation and removal of passivation film at the bottom of the trench, together with feature geometry. The RIE lag-eliminated trenches with constant area are obtained at a higher pressure of APC 70%. Deep and high aspect ratio silicon microstructures can be controlled by ICP etching with different pattern geometry.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Mechanics of Materials
- Mechanical Engineering
- Electrical and Electronic Engineering