TY - JOUR
T1 - Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture
AU - Lin, Ing Chao
AU - Chang, Da Wei
AU - Chen, Wei Jun
AU - Ke, Jian Ting
AU - Huang, Po Han
N1 - Funding Information:
Manuscript received October 12, 2018; revised February 19, 2019 and April 28, 2019; accepted May 2, 2019. Date of publication July 5, 2019; date of current version August 20, 2020. This work was supported in part by the Ministry of Science and Technology of Taiwan under Grant MOST 106-2221-E-006-027-MY3 and Grant 107-2221-E-006-044-MY3, and in part by the Industrial Technology Research Institute of Taiwan under Grant 52-B0-201503-01, Grant B5-10412-HQ-02, and Grant B5-10512-HQ-03. This paper was recommended by Associate Editor Z. Shao. (Corresponding author: Ing-Chao Lin.) I.-C. Lin, D.-W. Chang, W.-J. Chen, and J.-T. Ke are with the Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail: iclin@ mail.ncku.edu.tw; [email protected]; [email protected]; [email protected]).
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2020/9
Y1 - 2020/9
N2 - As cloud computing and big data applications become more popular, the demand for large capacity memory and data preservation in memory increases. Therefore, nonvolatile memory (NVM) with high capacity is being actively developed. A hybrid memory that comprises both NVM and DRAM and provides both high access speed and nonvolatility has become a major trend. However, compared to DRAM, NVM in the hybrid memory typically suffers from a shorter lifetime and higher latency. To improve the lifetime and address the latency issues associated with hybrid memory, we propose a global clean page first replacement (GCPF) to reduce the write operations to NVM. We also propose an index-aware multistream prefetcher (IAMSP) that considers the indexes of prefetch candidates individually so as to prefetch pages from NVM more accurately. Benchmarks with a large memory footprint are used to evaluate the proposed schemes. The experimental results show that GCPF enhances lifetime by 56.8% as compared to LRU, on average. When applying prefetching schemes on GCPF, the lifetime is insignificantly degraded. In addition, IAMSP reduces DRAM misses by 42.0% as compared to LRU, while a modern prefetcher that can change the prefetch degree dynamically only reduces DRAM misses by 38.0%, on average. When applying both GCPF and IAMSP, the average access latency can be reduced by 28.8% as compared to LRU.
AB - As cloud computing and big data applications become more popular, the demand for large capacity memory and data preservation in memory increases. Therefore, nonvolatile memory (NVM) with high capacity is being actively developed. A hybrid memory that comprises both NVM and DRAM and provides both high access speed and nonvolatility has become a major trend. However, compared to DRAM, NVM in the hybrid memory typically suffers from a shorter lifetime and higher latency. To improve the lifetime and address the latency issues associated with hybrid memory, we propose a global clean page first replacement (GCPF) to reduce the write operations to NVM. We also propose an index-aware multistream prefetcher (IAMSP) that considers the indexes of prefetch candidates individually so as to prefetch pages from NVM more accurately. Benchmarks with a large memory footprint are used to evaluate the proposed schemes. The experimental results show that GCPF enhances lifetime by 56.8% as compared to LRU, on average. When applying prefetching schemes on GCPF, the lifetime is insignificantly degraded. In addition, IAMSP reduces DRAM misses by 42.0% as compared to LRU, while a modern prefetcher that can change the prefetch degree dynamically only reduces DRAM misses by 38.0%, on average. When applying both GCPF and IAMSP, the average access latency can be reduced by 28.8% as compared to LRU.
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U2 - 10.1109/TCAD.2019.2925404
DO - 10.1109/TCAD.2019.2925404
M3 - Article
AN - SCOPUS:85068566585
SN - 0278-0070
VL - 39
SP - 1750
EP - 1763
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 9
M1 - 8756031
ER -