TY - GEN
T1 - Graph matching-based algorithms for array-based FPGA segmentation design and routing
AU - Lin, Jai Ming
AU - Pan, Song Ra
AU - Chang, Yao Wen
N1 - Publisher Copyright:
© 2003 IEEE.
Copyright:
Copyright 2016 Elsevier B.V., All rights reserved.
PY - 2003
Y1 - 2003
N2 - Architecture and CAD are closely related issues in FPGA design. Routing architecture design optimizes routability and facilitates router development; on the other hand, router design considers the specific properties of routing architectures to optimize the performance of the router. In this paper, we propose effective and efficient unified matching-based algorithms for array-based FPGA routing and segmentation design. For the segmentation design, we consider the similarity of input routing instances and formulate a net-matching problem to construct the optimal segmentation architecture. For the router design, we present a matching-based timing-driven routing algorithm which can consider a versatile set of routing segments. Experimental results show that our designed segmentations significantly outperform those used in commercially available FPGAs. For example, our designed segmentations achieve, on average, 14.6% and 19.7% improvements in routability, compared with those used in the Lucent Technologies ORCA 2C-series and the Xilinx XC4000E-series FPGAs, respectively.
AB - Architecture and CAD are closely related issues in FPGA design. Routing architecture design optimizes routability and facilitates router development; on the other hand, router design considers the specific properties of routing architectures to optimize the performance of the router. In this paper, we propose effective and efficient unified matching-based algorithms for array-based FPGA routing and segmentation design. For the segmentation design, we consider the similarity of input routing instances and formulate a net-matching problem to construct the optimal segmentation architecture. For the router design, we present a matching-based timing-driven routing algorithm which can consider a versatile set of routing segments. Experimental results show that our designed segmentations significantly outperform those used in commercially available FPGAs. For example, our designed segmentations achieve, on average, 14.6% and 19.7% improvements in routability, compared with those used in the Lucent Technologies ORCA 2C-series and the Xilinx XC4000E-series FPGAs, respectively.
UR - http://www.scopus.com/inward/record.url?scp=11244349270&partnerID=8YFLogxK
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U2 - 10.1109/ASPDAC.2003.1195136
DO - 10.1109/ASPDAC.2003.1195136
M3 - Conference contribution
AN - SCOPUS:11244349270
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 851
EP - 854
BT - Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Asia and South Pacific Design Automation Conference, ASP-DAC 2003
Y2 - 21 January 2003 through 24 January 2003
ER -