Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy

Research output: Contribution to journalConference article

3 Citations (Scopus)

Abstract

Polyphase channelizer is an important component of a subband adaptive filtering system. This paper presents efficient hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer, integrating optimizations at algorithmic, architectural and circuit level, At the algorithm level, a computationally efficient structure is derived. Tradeoffs between hardware complexity and system performance are explored during the fixed-point modeling of the system. A computational complexity reduction technique is also employed to reduce the complexity of the hardware architecture. Circuit-level optimizations, including an efficient commutator implementation, dual-VDD scheme and novel level-converting flip-flops, are also integrated. Simulation results show that the design consumes 352mW power with system throughput of 480 million samples per second (MSPS). A test chip has been submitted for fabrication to validate the proposed hardware architecture and VLSI design techniques.

Original languageEnglish
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume5
Publication statusPublished - 2004 Sep 27
EventProceedings - IEEE International Conference on Acoustics, Speech, and Signal Processing - Montreal, Que, Canada
Duration: 2004 May 172004 May 21

Fingerprint

Adaptive filtering
Hardware
Electric commutators
Networks (circuits)
Flip flop circuits
Computational complexity
Throughput
Fabrication

All Science Journal Classification (ASJC) codes

  • Software
  • Signal Processing
  • Electrical and Electronic Engineering

Cite this

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abstract = "Polyphase channelizer is an important component of a subband adaptive filtering system. This paper presents efficient hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer, integrating optimizations at algorithmic, architectural and circuit level, At the algorithm level, a computationally efficient structure is derived. Tradeoffs between hardware complexity and system performance are explored during the fixed-point modeling of the system. A computational complexity reduction technique is also employed to reduce the complexity of the hardware architecture. Circuit-level optimizations, including an efficient commutator implementation, dual-VDD scheme and novel level-converting flip-flops, are also integrated. Simulation results show that the design consumes 352mW power with system throughput of 480 million samples per second (MSPS). A test chip has been submitted for fabrication to validate the proposed hardware architecture and VLSI design techniques.",
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Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. / Wang, Yongtao; Mahmoodi, Hamid; Chiou, Lih-Yih; Choo, Hunsoo; Park, Jongsun; Jeong, Woopyo; Roy, Kaushik.

In: ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, Vol. 5, 27.09.2004.

Research output: Contribution to journalConference article

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T1 - Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

AU - Wang, Yongtao

AU - Mahmoodi, Hamid

AU - Chiou, Lih-Yih

AU - Choo, Hunsoo

AU - Park, Jongsun

AU - Jeong, Woopyo

AU - Roy, Kaushik

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AB - Polyphase channelizer is an important component of a subband adaptive filtering system. This paper presents efficient hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer, integrating optimizations at algorithmic, architectural and circuit level, At the algorithm level, a computationally efficient structure is derived. Tradeoffs between hardware complexity and system performance are explored during the fixed-point modeling of the system. A computational complexity reduction technique is also employed to reduce the complexity of the hardware architecture. Circuit-level optimizations, including an efficient commutator implementation, dual-VDD scheme and novel level-converting flip-flops, are also integrated. Simulation results show that the design consumes 352mW power with system throughput of 480 million samples per second (MSPS). A test chip has been submitted for fabrication to validate the proposed hardware architecture and VLSI design techniques.

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