This brief presents a hardware design for an energy-efficient, high-speed, and 1-D median filter. Existing architectures focus on operating speeds, thus resulting in redundant power dissipation. This brief presents an algorithm and mathematical model for controlling the clock signals attached to the circuit by analyzing the behavior of the filter, which immobilizes the data in registers and reduces not only signal transitions but also switching activities, thereby reducing the total dynamic power consumption. Furthermore, the proposed architecture provides high-speed computation. A median result can be produced in each clock cycle, and the maximum operating frequency performance is nearly independent of the filter size. The proposed architecture uses 90-nm process technology and experimental results show that the proposed method is more energy efficient than existing designs. The power consumption is reduced by 25% on average.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2018 Nov|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering