Hardware implementation of an image interpolation method with controllable sharpness

The technique of image scaling plays a critical role in the digital image processing applications for the coordination between different display devices. In this paper, an improved algorithm is proposed by using a controllable sharpness coefficient to obtain better resulting images under different scaling magnifications. In addition, a power saving module including a condition judgment mechanism is applied to reduce unnecessary power consumption as the scaling ratio increases. Experimental results show that the proposed architecture is still feasible for very large-scale integration implementation and effectively enhances the quality of image scaling. By using TSMC 0.13 m cell library, the synthesis results show that the circuit can achieve 300 MHz with 12.1k gate counts and cell area is 293293 m². The total power consumption is 6.75mW.