Hardware implementation of CMAC neural network with reduced storage requirement

Jar Shone Ker, Yau Hwang Kuo, Rong Chang Wen, Bin Da Liu

Research output: Contribution to journalArticlepeer-review

17 Citations (Scopus)


The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100%. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture.

Original languageEnglish
Pages (from-to)1545-1556
Number of pages12
JournalIEEE Transactions on Neural Networks
Issue number6
Publication statusPublished - 1997

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Science Applications
  • Computer Networks and Communications
  • Artificial Intelligence


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