Hardware/software codesign of resource constrained real-time systems

Chia Cheng Lo; Jung Guan Luo; Ming Der Shieh

doi:10.1109/IAS.2009.19

Hardware/software codesign of resource constrained real-time systems

Chia Cheng Lo, Jung Guan Luo, Ming Der Shieh

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

System-level design methods can provide a systematic and effective way of evaluating various design options, thus shortening the product development time. This paper relaxes the HC algorithm by considering the K best candidates in each clustering iteration to alleviate the possibility of being trapped in local minimum during hardware/software (HW/SW) partition. We also present an architecture mapping algorithm together with the defined sensitivity measure to further reduce the hardware requirement. Simulation results show that the complexity of exploration time can be greatly reduced with only little performance loss as compared to the exhaustive search. The proposed algorithm can thus provide a good compromise between exploration time and accuracy.

Original language	English
Title of host publication	5th International Conference on Information Assurance and Security, IAS 2009
Pages	177-180
Number of pages	4
DOIs	https://doi.org/10.1109/IAS.2009.19
Publication status	Published - 2009 Dec 1
Event	5th International Conference on Information Assurance and Security, IAS 2009 - Xian, China Duration: 2009 Aug 18 → 2009 Sep 20

Publication series

Name	5th International Conference on Information Assurance and Security, IAS 2009
Volume	1

Other

Other	5th International Conference on Information Assurance and Security, IAS 2009
Country/Territory	China
City	Xian
Period	09-08-18 → 09-09-20

All Science Journal Classification (ASJC) codes

Computational Theory and Mathematics
Computer Science Applications
Hardware and Architecture
Software

Access to Document

10.1109/IAS.2009.19

Cite this

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title = "Hardware/software codesign of resource constrained real-time systems",

abstract = "System-level design methods can provide a systematic and effective way of evaluating various design options, thus shortening the product development time. This paper relaxes the HC algorithm by considering the K best candidates in each clustering iteration to alleviate the possibility of being trapped in local minimum during hardware/software (HW/SW) partition. We also present an architecture mapping algorithm together with the defined sensitivity measure to further reduce the hardware requirement. Simulation results show that the complexity of exploration time can be greatly reduced with only little performance loss as compared to the exhaustive search. The proposed algorithm can thus provide a good compromise between exploration time and accuracy.",

author = "Lo, {Chia Cheng} and Luo, {Jung Guan} and Shieh, {Ming Der}",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/IAS.2009.19",

language = "English",

isbn = "9780769537443",

series = "5th International Conference on Information Assurance and Security, IAS 2009",

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booktitle = "5th International Conference on Information Assurance and Security, IAS 2009",

note = "5th International Conference on Information Assurance and Security, IAS 2009 ; Conference date: 18-08-2009 Through 20-09-2009",

}

Lo, CC, Luo, JG & Shieh, MD 2009, Hardware/software codesign of resource constrained real-time systems. in 5th International Conference on Information Assurance and Security, IAS 2009., 5283835, 5th International Conference on Information Assurance and Security, IAS 2009, vol. 1, pp. 177-180, 5th International Conference on Information Assurance and Security, IAS 2009, Xian, China, 09-08-18. https://doi.org/10.1109/IAS.2009.19

Hardware/software codesign of resource constrained real-time systems. / Lo, Chia Cheng; Luo, Jung Guan; Shieh, Ming Der.

5th International Conference on Information Assurance and Security, IAS 2009. 2009. p. 177-180 5283835 (5th International Conference on Information Assurance and Security, IAS 2009; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - System-level design methods can provide a systematic and effective way of evaluating various design options, thus shortening the product development time. This paper relaxes the HC algorithm by considering the K best candidates in each clustering iteration to alleviate the possibility of being trapped in local minimum during hardware/software (HW/SW) partition. We also present an architecture mapping algorithm together with the defined sensitivity measure to further reduce the hardware requirement. Simulation results show that the complexity of exploration time can be greatly reduced with only little performance loss as compared to the exhaustive search. The proposed algorithm can thus provide a good compromise between exploration time and accuracy.

AB - System-level design methods can provide a systematic and effective way of evaluating various design options, thus shortening the product development time. This paper relaxes the HC algorithm by considering the K best candidates in each clustering iteration to alleviate the possibility of being trapped in local minimum during hardware/software (HW/SW) partition. We also present an architecture mapping algorithm together with the defined sensitivity measure to further reduce the hardware requirement. Simulation results show that the complexity of exploration time can be greatly reduced with only little performance loss as compared to the exhaustive search. The proposed algorithm can thus provide a good compromise between exploration time and accuracy.

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Y2 - 18 August 2009 through 20 September 2009

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Hardware/software codesign of resource constrained real-time systems

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