Hazard-free synthesis and decomposition of asynchronous circuits

Ren Der Chen, Jer Min Jou, Yeu Horng Shiau

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we solve the problems of hazard-free synthesis and decomposition of asynchronous speed-independent circuits for technology mapping. All high fanin gates are decomposed into gates that can be implemented by the gate library. We first analyze the conditions where hazards may occur during decomposition and then give corresponding strategies to solve them. All the proposed algorithms have been implemented and applied to the asynchronous benchmarks to verify their correctness. Experimental results show that less area is required in our final implementations.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages185-188
Number of pages4
ISBN (Electronic)078035012X
DOIs
Publication statusPublished - 1999
Event4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 - Wanchai, Hong Kong
Duration: 1999 Jan 181999 Jan 21

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume1999-January

Conference

Conference4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Country/TerritoryHong Kong
CityWanchai
Period99-01-1899-01-21

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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