Heterogeneous integration of nano devices on Si CMOS platform

This paper outlines the limits on traditional scaling of CMOS and beyond, as well as the possibilities of introducing novel materials, their devices and the organization of these structures. From these organized structures, new local information processing architectures beyond CMOS may be possible. In addition to achieving continuous improvement of performance following Moores Law, another benefit of integration is to have more functions on a Si platform. Thus, the potential of heterogeneous integration of self-assembly wires, dots, and molecules, with nanometer scale feature sizes on a Si CMOS platform may lead to future integrated nanosystems, incorporating many functions beyond traditional electronics. Nanostructures enable reduction of defects and they may be formed without rigid conformation to the crystalline structure of the substrates, or in other words, they are relatively free from constraint of the crystalline substrates. Thus, high performance devices and circuits may be integrated in a large area. One of the major issues for continuous increase of integration level is the increase of power dissipation per unit area on chip. We examine this critical issue of integrated circuits from a fundamental point of view of power dissipation. In order to alleviate the power dissipation issue, we study locally active devices, which may be built from homogeneous to form computational systems. Systems, such as cellular automata, cellular nonlinear networks, and other similar architectures, may be explored for low power application using nanometer scale devices and their integration.