HfLaON n-MOSFETs using a low work function HfSix gate

C. F. Cheng; C. H. Wu; N. C. Su; S. J. Wang; S. P. McAlister; Albert Chin

doi:10.1109/LED.2007.909843

HfLaON n-MOSFETs using a low work function HfSi_x gate

C. F. Cheng, C. H. Wu, N. C. Su, S. J. Wang, S. P. McAlister, Albert Chin

Institute of Microelectronics

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

At a 1.2-nm equivalent oxide thickness, HfSi_x/Hf_0.7 La_0.3ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm²/(V · s). These self-aligned and gate-first HfSi_x/Hf_0.7La_0.3ON n-MOSFETs were processed using standard ion implantation and 1000-°C rapid thermal annealing,making them fully compatible with current very large scale integration fabrication lines.

Original language	English
Pages (from-to)	1092-1094
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	28
Issue number	12
DOIs	https://doi.org/10.1109/LED.2007.909843
Publication status	Published - 2007 Dec

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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@article{f132c4ed5f2f46d1b6a57654f33520ec,

title = "HfLaON n-MOSFETs using a low work function HfSix gate",

abstract = "At a 1.2-nm equivalent oxide thickness, HfSix/Hf0.7 La0.3ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm2/(V · s). These self-aligned and gate-first HfSix/Hf0.7La0.3ON n-MOSFETs were processed using standard ion implantation and 1000-°C rapid thermal annealing,making them fully compatible with current very large scale integration fabrication lines.",

author = "Cheng, {C. F.} and Wu, {C. H.} and Su, {N. C.} and Wang, {S. J.} and McAlister, {S. P.} and Albert Chin",

note = "Funding Information: Manuscript received July 24, 2007; revised August 28, 2007. This work was supported in part by National Science Council 95-2221-E-009-275 and Technology Development Program for Academia, Department of Industrial Technology, Ministry of Economic Affairs 94-EC-17-A-01-S1-047 of Taiwan. The review of this letter was arranged by Editor B. Yu.",

year = "2007",

month = dec,

doi = "10.1109/LED.2007.909843",

language = "English",

volume = "28",

pages = "1092--1094",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - HfLaON n-MOSFETs using a low work function HfSix gate

AU - Cheng, C. F.

AU - Wu, C. H.

AU - Su, N. C.

AU - Wang, S. J.

AU - McAlister, S. P.

AU - Chin, Albert

N1 - Funding Information: Manuscript received July 24, 2007; revised August 28, 2007. This work was supported in part by National Science Council 95-2221-E-009-275 and Technology Development Program for Academia, Department of Industrial Technology, Ministry of Economic Affairs 94-EC-17-A-01-S1-047 of Taiwan. The review of this letter was arranged by Editor B. Yu.

PY - 2007/12

Y1 - 2007/12

N2 - At a 1.2-nm equivalent oxide thickness, HfSix/Hf0.7 La0.3ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm2/(V · s). These self-aligned and gate-first HfSix/Hf0.7La0.3ON n-MOSFETs were processed using standard ion implantation and 1000-°C rapid thermal annealing,making them fully compatible with current very large scale integration fabrication lines.

AB - At a 1.2-nm equivalent oxide thickness, HfSix/Hf0.7 La0.3ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm2/(V · s). These self-aligned and gate-first HfSix/Hf0.7La0.3ON n-MOSFETs were processed using standard ion implantation and 1000-°C rapid thermal annealing,making them fully compatible with current very large scale integration fabrication lines.

UR - http://www.scopus.com/inward/record.url?scp=36549077661&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=36549077661&partnerID=8YFLogxK

U2 - 10.1109/LED.2007.909843

DO - 10.1109/LED.2007.909843

M3 - Article

AN - SCOPUS:36549077661

VL - 28

SP - 1092

EP - 1094

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 12