Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core

Jin Hua Hong, Chung Hung Tsai, Cheng Wen Wu

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)

Abstract

An IEEE 1149.5 module test and maintenance (MTM) bus slave module interface core is presented, which is used for direct access from the system bus to the IEEE 1149.1 chip-level or on-chip buses to facilitate hierarchical system test and diagnosis. The hierarchical test methodology also is presented, which is applicable to the system-on-chip environment. All the standard 1149.1 instructions, such as SAMPLE/PRELOAD, EXTEST, BYPASS, and even RUNBIST, can be performed within three 1149.5 read/write-data message cycles. The messages are transmitted between the MTM-bus master module (M-module) and the slave module (S-module). We adopt the full test access port control method to activate the 1149.1 boundary-scan paths via the 1149.5 MTM-bus. Our S-module interface circuit implements 16 CORE commands and one read/write-data command. It has been prototyped using a field-programmable gate array chip and implemented by a full-custom chip. Hierarchical test of multiple 1149.1 compatible boards has been experimented and verified.

Original languageEnglish
Pages (from-to)503-516
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume8
Issue number5
DOIs
Publication statusPublished - 2000 Oct 1
Event11th International Symposium on System-Level Synthesis and Design (ISS'98) - Hsinchu, Taiwan
Duration: 1998 Dec 21998 Dec 4

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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