Abstract
An IEEE 1149.5 module test and maintenance (MTM) bus slave module interface core is presented, which is used for direct access from the system bus to the IEEE 1149.1 chip-level or on-chip buses to facilitate hierarchical system test and diagnosis. The hierarchical test methodology also is presented, which is applicable to the system-on-chip environment. All the standard 1149.1 instructions, such as SAMPLE/PRELOAD, EXTEST, BYPASS, and even RUNBIST, can be performed within three 1149.5 read/write-data message cycles. The messages are transmitted between the MTM-bus master module (M-module) and the slave module (S-module). We adopt the full test access port control method to activate the 1149.1 boundary-scan paths via the 1149.5 MTM-bus. Our S-module interface circuit implements 16 CORE commands and one read/write-data command. It has been prototyped using a field-programmable gate array chip and implemented by a full-custom chip. Hierarchical test of multiple 1149.1 compatible boards has been experimented and verified.
| Original language | English |
|---|---|
| Pages (from-to) | 503-516 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 8 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 2000 Oct 1 |
| Event | 11th International Symposium on System-Level Synthesis and Design (ISS'98) - Hsinchu, Taiwan Duration: 1998 Dec 2 → 1998 Dec 4 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
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Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core. / Hong, Jin Hua; Tsai, Chung Hung; Wu, Cheng Wen.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 5, 01.10.2000, p. 503-516.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core
AU - Hong, Jin Hua
AU - Tsai, Chung Hung
AU - Wu, Cheng Wen
PY - 2000/10/1
Y1 - 2000/10/1
N2 - An IEEE 1149.5 module test and maintenance (MTM) bus slave module interface core is presented, which is used for direct access from the system bus to the IEEE 1149.1 chip-level or on-chip buses to facilitate hierarchical system test and diagnosis. The hierarchical test methodology also is presented, which is applicable to the system-on-chip environment. All the standard 1149.1 instructions, such as SAMPLE/PRELOAD, EXTEST, BYPASS, and even RUNBIST, can be performed within three 1149.5 read/write-data message cycles. The messages are transmitted between the MTM-bus master module (M-module) and the slave module (S-module). We adopt the full test access port control method to activate the 1149.1 boundary-scan paths via the 1149.5 MTM-bus. Our S-module interface circuit implements 16 CORE commands and one read/write-data command. It has been prototyped using a field-programmable gate array chip and implemented by a full-custom chip. Hierarchical test of multiple 1149.1 compatible boards has been experimented and verified.
AB - An IEEE 1149.5 module test and maintenance (MTM) bus slave module interface core is presented, which is used for direct access from the system bus to the IEEE 1149.1 chip-level or on-chip buses to facilitate hierarchical system test and diagnosis. The hierarchical test methodology also is presented, which is applicable to the system-on-chip environment. All the standard 1149.1 instructions, such as SAMPLE/PRELOAD, EXTEST, BYPASS, and even RUNBIST, can be performed within three 1149.5 read/write-data message cycles. The messages are transmitted between the MTM-bus master module (M-module) and the slave module (S-module). We adopt the full test access port control method to activate the 1149.1 boundary-scan paths via the 1149.5 MTM-bus. Our S-module interface circuit implements 16 CORE commands and one read/write-data command. It has been prototyped using a field-programmable gate array chip and implemented by a full-custom chip. Hierarchical test of multiple 1149.1 compatible boards has been experimented and verified.
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U2 - 10.1109/92.894154
DO - 10.1109/92.894154
M3 - Conference article
AN - SCOPUS:0034289925
VL - 8
SP - 503
EP - 516
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 5
ER -