Hierarchical test control architecture for core based design

Kuen Jong Lee, Cheng I. Huang

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

Recently system-on-chip (SOC) design based on IP cores has become the trend of IC design. To prevent the testing problem from becoming the bottleneck of the cored-based design, the IEEE P1500 Working Group is defining a test standard that can greatly simplify the core test problem. In this paper, we propose a new core-based test architecture that can support the IEEE P1500 cores as well as the well-accepted IEEE 1149.1 cores. Both the serial and parallel testing capabilities are provided. Moreover, a new hierarchical test control mechanism has been developed that facilitates the hierarchical test access for deeply embedded cores.

Original languageEnglish
Pages (from-to)248-253
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 2000 Dec 1
Event9th Asian Test Symposium - Taipei, Taiwan
Duration: 2000 Dec 42000 Dec 6

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Testing
Integrated circuit design
System-on-chip
Intellectual property core

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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Hierarchical test control architecture for core based design. / Lee, Kuen Jong; Huang, Cheng I.

In: Proceedings of the Asian Test Symposium, 01.12.2000, p. 248-253.

Research output: Contribution to journalConference article

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