Abstract
Recently system-on-chip (SOC) design based on IP cores has become the trend of IC design. To prevent the testing problem from becoming the bottleneck of the cored-based design, the IEEE P1500 Working Group is defining a test standard that can greatly simplify the core test problem. In this paper, we propose a new core-based test architecture that can support the IEEE P1500 cores as well as the well-accepted IEEE 1149.1 cores. Both the serial and parallel testing capabilities are provided. Moreover, a new hierarchical test control mechanism has been developed that facilitates the hierarchical test access for deeply embedded cores.
| Original language | English |
|---|---|
| Pages (from-to) | 248-253 |
| Number of pages | 6 |
| Journal | Proceedings of the Asian Test Symposium |
| Publication status | Published - 2000 Dec 1 |
| Event | 9th Asian Test Symposium - Taipei, Taiwan Duration: 2000 Dec 4 → 2000 Dec 6 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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Hierarchical test control architecture for core based design. / Lee, Kuen Jong; Huang, Cheng I.
In: Proceedings of the Asian Test Symposium, 01.12.2000, p. 248-253.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - Hierarchical test control architecture for core based design
AU - Lee, Kuen Jong
AU - Huang, Cheng I.
PY - 2000/12/1
Y1 - 2000/12/1
N2 - Recently system-on-chip (SOC) design based on IP cores has become the trend of IC design. To prevent the testing problem from becoming the bottleneck of the cored-based design, the IEEE P1500 Working Group is defining a test standard that can greatly simplify the core test problem. In this paper, we propose a new core-based test architecture that can support the IEEE P1500 cores as well as the well-accepted IEEE 1149.1 cores. Both the serial and parallel testing capabilities are provided. Moreover, a new hierarchical test control mechanism has been developed that facilitates the hierarchical test access for deeply embedded cores.
AB - Recently system-on-chip (SOC) design based on IP cores has become the trend of IC design. To prevent the testing problem from becoming the bottleneck of the cored-based design, the IEEE P1500 Working Group is defining a test standard that can greatly simplify the core test problem. In this paper, we propose a new core-based test architecture that can support the IEEE P1500 cores as well as the well-accepted IEEE 1149.1 cores. Both the serial and parallel testing capabilities are provided. Moreover, a new hierarchical test control mechanism has been developed that facilitates the hierarchical test access for deeply embedded cores.
UR - http://www.scopus.com/inward/record.url?scp=0034497148&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0034497148&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0034497148
SP - 248
EP - 253
JO - Proceedings of the Asian Test Symposium
JF - Proceedings of the Asian Test Symposium
SN - 1081-7735
ER -