High accuracy approximate multiplier with error correction

Chia Hao Lin, Ing-Chao Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

88 Citations (Scopus)

Abstract

Approximate computing has gained significant attention due to the popularity of multimedia applications. In this paper, we propose a novel inaccurate 4:2 counter that can effectively reduce the partial product stages of the Wallace Multiplier. Compared to the normal Wallace multiplier, our proposed multiplier can reduce 10.74% of power consumption and 9.8% of delay on average, with an error rate from 0.2% to 13.76% The accuracy of amplitude is higher than 99% In addition, we further enhance the design with error-correction units to provide accurate results. The experimental results show that the extra power consumption of correct units is lower than 6% on average. Compared to the normal Wallace multiplier, the average latency of our proposed multiplier with EDC is 6% faster when the bit-width is 32, and the power consumption is still 10% lower than that of the Wallace multiplier.

Original languageEnglish
Title of host publication2013 IEEE 31st International Conference on Computer Design, ICCD 2013
PublisherIEEE Computer Society
Pages33-38
Number of pages6
ISBN (Print)9781479929870
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 IEEE 31st International Conference on Computer Design, ICCD 2013 - Asheville, NC, United States
Duration: 2013 Oct 62013 Oct 9

Publication series

Name2013 IEEE 31st International Conference on Computer Design, ICCD 2013

Other

Other2013 IEEE 31st International Conference on Computer Design, ICCD 2013
CountryUnited States
CityAsheville, NC
Period13-10-0613-10-09

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture

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