High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices

Meng Hsueh Chiang, Keunwoo Kim, Ching Te Chuang, Christophe Tretz

Research output: Contribution to journalArticlepeer-review

68 Citations (Scopus)

Abstract

Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations.

Original languageEnglish
Pages (from-to)2370-2377
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume53
Issue number9
DOIs
Publication statusPublished - 2006 Sep 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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