TY - GEN
T1 - High-density SRAM voltage scaling enabled by inserted-oxide FinFET technology
AU - Wu, Yi Ting
AU - Chiang, Meng Hsueh
AU - Chen, Jone F.
AU - Ding, Fei
AU - Connelly, Daniel
AU - Liu, Tsu Jae King
N1 - Funding Information:
This work was partially supported by the Ministry of Science and Technology of Taiwan under Grant no. 104-2911-I-006-534 and 105-2911-I-006-508.
Publisher Copyright:
© 2017 IEEE.
PY - 2018/3/7
Y1 - 2018/3/7
N2 - A scheme to precisely adjust the drive strength of an inserted-oxide FinFET (iFinFET), to enhance the manufacturing yield of a minimally sized six-transistor (6-T) SRAM cell, is proposed. Specifically, the top nanowire (NW) channel in an iFinFET can be made to be essentially non-conducting by ion implantation to increase its threshold voltage, and the position of the inserted-oxide layer can be optimized for maximum cell yield at low operating voltage. Via three-dimensional (3-D) device simulations and a calibrated compact model, this scheme is projected to lower the minimum operating voltage (Vmin) of a minimally sized 6-T SRAM cell.
AB - A scheme to precisely adjust the drive strength of an inserted-oxide FinFET (iFinFET), to enhance the manufacturing yield of a minimally sized six-transistor (6-T) SRAM cell, is proposed. Specifically, the top nanowire (NW) channel in an iFinFET can be made to be essentially non-conducting by ion implantation to increase its threshold voltage, and the position of the inserted-oxide layer can be optimized for maximum cell yield at low operating voltage. Via three-dimensional (3-D) device simulations and a calibrated compact model, this scheme is projected to lower the minimum operating voltage (Vmin) of a minimally sized 6-T SRAM cell.
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U2 - 10.1109/S3S.2017.8309217
DO - 10.1109/S3S.2017.8309217
M3 - Conference contribution
AN - SCOPUS:85047625901
T3 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
SP - 1
EP - 3
BT - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Y2 - 16 October 2017 through 18 October 2017
ER -