High-performance NTT architecture for large integer multiplication

Jheng Hao Ye, Ming Der Shieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents an efficient architecture of number Theoretical transform (NTT), targeting at fulfilling large integer multiplication for fully homomorphic encryption applications. A systematic memory management scheme is proposed for the pipelined shared-memory NTT architecture implemented with mixed-radix multi-path delay commutators (MDCs). The presented data relocation scheme along with the MDC can be applied to merge multiple banks with single-port memory for further reducing the area requirement. Experimental results show that a 1,179,648-bit multiplier implemented by the proposed solution, including seamless data transfer among the building blocks, can lead to more than 39.8% area reduction with even a lower computational time as compared with the related works.

Original languageEnglish
Title of host publication2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538642603
DOIs
Publication statusPublished - 2018 Jun 5
Event2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan
Duration: 2018 Apr 162018 Apr 19

Publication series

Name2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Other

Other2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
CountryTaiwan
CityHsinchu
Period18-04-1618-04-19

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Control and Optimization
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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