High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application

Chun Yu Chen, Jyi Tsong Lin, Meng Hsueh Chiang, Keunwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

Comparison of junctionless and conventional nanowire FETs is presented. Our numerical simulation results suggest that though the junctionless device suffers low drive current due to its accumulation nature, it has an advantage in scalability. Relaxed wire diameter requirement is predicted for the junctionless case. More interestingly, it shows a great potential in ultra-low power subthreshold logic application due to superior speed, as compared with the conventional structure.

Original languageEnglish
Title of host publication2010 IEEE International SOI Conference, SOI 2010
DOIs
Publication statusPublished - 2010 Dec 30
Event2010 IEEE International Silicon on Insulator Conference, SOI 2010 - San Diego, CA, United States
Duration: 2010 Oct 112010 Oct 14

Publication series

NameProceedings - IEEE International SOI Conference
ISSN (Print)1078-621X

Other

Other2010 IEEE International Silicon on Insulator Conference, SOI 2010
CountryUnited States
CitySan Diego, CA
Period10-10-1110-10-14

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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