High performance VLSI architecture design for 10/100 Mbps Ethernet switching fabric

Ming Haw Sheu, Chung-Ho Chen, Ming-Der Shieh, Tzung Shiue Li

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

We present the design and implementation of an integrated 10 Mbps and 100 Mbps Ethernet switching hub controller. The controller supports two 100 Mbps and eight 10 Mbps Ethernet ports. All ports can transmit data in half or full duplex mode. Through a high-bandwidth shared bus, the architecture supports two switching modes: cut-through and store-and-forward. We design a snooping bus to support the cut-through switching mode for on-the-fly forwarding. The controller has been implemented as a single chip based on the 0.6 μm CMOS technology. It consumes about 5300*5500 μm2 in area with a 208-pin package.

Original languageEnglish
Pages (from-to)26-27
Number of pages2
JournalDigest of Technical Papers - IEEE International Conference on Consumer Electronics
Publication statusPublished - 1998 Jan 1
EventProceedings of the 1998 17th Conference on Consumer Electronics - Los Angeles, CA, USA
Duration: 1998 Jun 21998 Jun 4

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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