High performance VLSI architecture design for 10/100 Mbps Ethernet switching fabric

Ming Haw Sheu; Chung-Ho Chen; Ming-Der Shieh; Tzung Shiue Li

High performance VLSI architecture design for 10/100 Mbps Ethernet switching fabric

Ming Haw Sheu, Chung-Ho Chen, Ming-Der Shieh, Tzung Shiue Li

Research output: Contribution to journal › Conference article › peer-review

Abstract

We present the design and implementation of an integrated 10 Mbps and 100 Mbps Ethernet switching hub controller. The controller supports two 100 Mbps and eight 10 Mbps Ethernet ports. All ports can transmit data in half or full duplex mode. Through a high-bandwidth shared bus, the architecture supports two switching modes: cut-through and store-and-forward. We design a snooping bus to support the cut-through switching mode for on-the-fly forwarding. The controller has been implemented as a single chip based on the 0.6 μm CMOS technology. It consumes about 5300*5500 μm² in area with a 208-pin package.

Original language	English
Pages (from-to)	26-27
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
Publication status	Published - 1998 Jan 1
Event	Proceedings of the 1998 17th Conference on Consumer Electronics - Los Angeles, CA, USA Duration: 1998 Jun 2 → 1998 Jun 4

All Science Journal Classification (ASJC) codes

Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

Cite this

@article{e6e6e6deb18f42de87577d0f75f37562,

title = "High performance VLSI architecture design for 10/100 Mbps Ethernet switching fabric",

abstract = "We present the design and implementation of an integrated 10 Mbps and 100 Mbps Ethernet switching hub controller. The controller supports two 100 Mbps and eight 10 Mbps Ethernet ports. All ports can transmit data in half or full duplex mode. Through a high-bandwidth shared bus, the architecture supports two switching modes: cut-through and store-and-forward. We design a snooping bus to support the cut-through switching mode for on-the-fly forwarding. The controller has been implemented as a single chip based on the 0.6 μm CMOS technology. It consumes about 5300*5500 μm2 in area with a 208-pin package.",

author = "Sheu, {Ming Haw} and Chung-Ho Chen and Ming-Der Shieh and Li, {Tzung Shiue}",

year = "1998",

month = jan,

day = "1",

language = "English",

pages = "26--27",

journal = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

issn = "0747-668X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1998 17th Conference on Consumer Electronics ; Conference date: 02-06-1998 Through 04-06-1998",

}

TY - JOUR

T1 - High performance VLSI architecture design for 10/100 Mbps Ethernet switching fabric

AU - Sheu, Ming Haw

AU - Chen, Chung-Ho

AU - Shieh, Ming-Der

AU - Li, Tzung Shiue

PY - 1998/1/1

Y1 - 1998/1/1

N2 - We present the design and implementation of an integrated 10 Mbps and 100 Mbps Ethernet switching hub controller. The controller supports two 100 Mbps and eight 10 Mbps Ethernet ports. All ports can transmit data in half or full duplex mode. Through a high-bandwidth shared bus, the architecture supports two switching modes: cut-through and store-and-forward. We design a snooping bus to support the cut-through switching mode for on-the-fly forwarding. The controller has been implemented as a single chip based on the 0.6 μm CMOS technology. It consumes about 5300*5500 μm2 in area with a 208-pin package.

AB - We present the design and implementation of an integrated 10 Mbps and 100 Mbps Ethernet switching hub controller. The controller supports two 100 Mbps and eight 10 Mbps Ethernet ports. All ports can transmit data in half or full duplex mode. Through a high-bandwidth shared bus, the architecture supports two switching modes: cut-through and store-and-forward. We design a snooping bus to support the cut-through switching mode for on-the-fly forwarding. The controller has been implemented as a single chip based on the 0.6 μm CMOS technology. It consumes about 5300*5500 μm2 in area with a 208-pin package.

UR - http://www.scopus.com/inward/record.url?scp=0031626207&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031626207&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0031626207

SP - 26

EP - 27

JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

SN - 0747-668X

T2 - Proceedings of the 1998 17th Conference on Consumer Electronics

Y2 - 2 June 1998 through 4 June 1998

ER -

High performance VLSI architecture design for 10/100 Mbps Ethernet switching fabric

Abstract

All Science Journal Classification (ASJC) codes

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