High-performance VLSI architecture for maps criterion motion estimation

Ming-Der Shieh, Ming Hwa Sheu, Yu Chin Hsu, Jia Lin Sheu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a novel block-matching criterion called partitioned mean absolute error of projective sum (PMAPS) is proposed to reduce the computational complexity of block-based motion estimation. With approximate prediction quality and compression efficiency as the mean absolute difference (MAD), the PMAPS can save about 50% computational load of MAD by the presented fast algorithm. Based on its simple and regular properties, a versatile 1-D array architecture and its VLSI implementation are developed with the characteristics of 100% hardware utilization, simple control, and flexible and modular structures.

Original languageEnglish
Title of host publicationMidwest Symposium on Circuits and Systems
Editors Anon
PublisherIEEE
Pages1221-1224
Number of pages4
Volume2
Publication statusPublished - 1997
EventProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Sacramento, CA, USA
Duration: 1997 Aug 31997 Aug 6

Other

OtherProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
CitySacramento, CA, USA
Period97-08-0397-08-06

Fingerprint

Motion estimation
Computational complexity
Hardware

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Shieh, M-D., Sheu, M. H., Hsu, Y. C., & Sheu, J. L. (1997). High-performance VLSI architecture for maps criterion motion estimation. In Anon (Ed.), Midwest Symposium on Circuits and Systems (Vol. 2, pp. 1221-1224). IEEE.
Shieh, Ming-Der ; Sheu, Ming Hwa ; Hsu, Yu Chin ; Sheu, Jia Lin. / High-performance VLSI architecture for maps criterion motion estimation. Midwest Symposium on Circuits and Systems. editor / Anon. Vol. 2 IEEE, 1997. pp. 1221-1224
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Shieh, M-D, Sheu, MH, Hsu, YC & Sheu, JL 1997, High-performance VLSI architecture for maps criterion motion estimation. in Anon (ed.), Midwest Symposium on Circuits and Systems. vol. 2, IEEE, pp. 1221-1224, Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, 97-08-03.

High-performance VLSI architecture for maps criterion motion estimation. / Shieh, Ming-Der; Sheu, Ming Hwa; Hsu, Yu Chin; Sheu, Jia Lin.

Midwest Symposium on Circuits and Systems. ed. / Anon. Vol. 2 IEEE, 1997. p. 1221-1224.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Shieh M-D, Sheu MH, Hsu YC, Sheu JL. High-performance VLSI architecture for maps criterion motion estimation. In Anon, editor, Midwest Symposium on Circuits and Systems. Vol. 2. IEEE. 1997. p. 1221-1224