High-performance VLSI architecture for maps criterion motion estimation

Ming Der Shieh; Ming Hwa Sheu; Yu Chin Hsu; Jia Lin Sheu

High-performance VLSI architecture for maps criterion motion estimation

Ming Der Shieh
, Ming Hwa Sheu
, Yu Chin Hsu
, Jia Lin Sheu

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

In this paper, a novel block-matching criterion called partitioned mean absolute error of projective sum (PMAPS) is proposed to reduce the computational complexity of block-based motion estimation. With approximate prediction quality and compression efficiency as the mean absolute difference (MAD), the PMAPS can save about 50% computational load of MAD by the presented fast algorithm. Based on its simple and regular properties, a versatile 1-D array architecture and its VLSI implementation are developed with the characteristics of 100% hardware utilization, simple control, and flexible and modular structures.

Original language	English
Pages	1221-1224
Number of pages	4
Publication status	Published - 1997
Event	Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Sacramento, CA, USA Duration: 1997 Aug 3 → 1997 Aug 6

Other

Other	Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
City	Sacramento, CA, USA
Period	97-08-03 → 97-08-06

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "High-performance VLSI architecture for maps criterion motion estimation",

abstract = "In this paper, a novel block-matching criterion called partitioned mean absolute error of projective sum (PMAPS) is proposed to reduce the computational complexity of block-based motion estimation. With approximate prediction quality and compression efficiency as the mean absolute difference (MAD), the PMAPS can save about 50\% computational load of MAD by the presented fast algorithm. Based on its simple and regular properties, a versatile 1-D array architecture and its VLSI implementation are developed with the characteristics of 100\% hardware utilization, simple control, and flexible and modular structures.",

author = "Shieh, \{Ming Der\} and Sheu, \{Ming Hwa\} and Hsu, \{Yu Chin\} and Sheu, \{Jia Lin\}",

year = "1997",

language = "English",

pages = "1221--1224",

note = "Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) ; Conference date: 03-08-1997 Through 06-08-1997",

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T1 - High-performance VLSI architecture for maps criterion motion estimation

AU - Shieh, Ming Der

AU - Sheu, Ming Hwa

AU - Hsu, Yu Chin

AU - Sheu, Jia Lin

PY - 1997

Y1 - 1997

N2 - In this paper, a novel block-matching criterion called partitioned mean absolute error of projective sum (PMAPS) is proposed to reduce the computational complexity of block-based motion estimation. With approximate prediction quality and compression efficiency as the mean absolute difference (MAD), the PMAPS can save about 50% computational load of MAD by the presented fast algorithm. Based on its simple and regular properties, a versatile 1-D array architecture and its VLSI implementation are developed with the characteristics of 100% hardware utilization, simple control, and flexible and modular structures.

AB - In this paper, a novel block-matching criterion called partitioned mean absolute error of projective sum (PMAPS) is proposed to reduce the computational complexity of block-based motion estimation. With approximate prediction quality and compression efficiency as the mean absolute difference (MAD), the PMAPS can save about 50% computational load of MAD by the presented fast algorithm. Based on its simple and regular properties, a versatile 1-D array architecture and its VLSI implementation are developed with the characteristics of 100% hardware utilization, simple control, and flexible and modular structures.

UR - https://www.scopus.com/pages/publications/0031374784

UR - https://www.scopus.com/pages/publications/0031374784#tab=citedBy

M3 - Paper

AN - SCOPUS:0031374784

SP - 1221

EP - 1224

T2 - Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2)

Y2 - 3 August 1997 through 6 August 1997

ER -

High-performance VLSI architecture for maps criterion motion estimation

Abstract

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All Science Journal Classification (ASJC) codes

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