High-reliability programmable CMOS WTA/LTA circuit of O(N) complexity using a single comparator

Y. C. Hung, Bin-Da Liu

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A high reliability complementary metal-oxide semiconductor (CMOS) winner-takes-all/ loser-takes-all circuit of O(N) complexity with programmable capability is designed. Based on the proposed architecture, the precision of the circuit is independent of the number of inputs. This circuit is easily programmed for WTA or LTA function by an enable signal, without modifying the circuit structure or preprocessing the input variables. Since the circuit contains only simple logic gates and a single comparator, it is tolerant of VLSI process variations. The response time of the circuit increases linearly with the number of inputs. The input signal range of the circuit allows rail-to-rail (0-VDD) operation. The supply voltage ranges from 2.7V to 5V. An experimental chip with six inputs was fabricated using 0.5-μm CMOS double-poly double-metal technology. The results show that a cell is either a winner or a loser if its input voltage is larger or smaller than the other cells by 10 mV.

Original languageEnglish
Pages (from-to)579-586
Number of pages8
JournalIEE Proceedings: Circuits, Devices and Systems
Volume151
Issue number6
DOIs
Publication statusPublished - 2004 Dec 1

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Networks (circuits)
Metals
Rails
Logic gates
Electric potential
Oxide semiconductors

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "A high reliability complementary metal-oxide semiconductor (CMOS) winner-takes-all/ loser-takes-all circuit of O(N) complexity with programmable capability is designed. Based on the proposed architecture, the precision of the circuit is independent of the number of inputs. This circuit is easily programmed for WTA or LTA function by an enable signal, without modifying the circuit structure or preprocessing the input variables. Since the circuit contains only simple logic gates and a single comparator, it is tolerant of VLSI process variations. The response time of the circuit increases linearly with the number of inputs. The input signal range of the circuit allows rail-to-rail (0-VDD) operation. The supply voltage ranges from 2.7V to 5V. An experimental chip with six inputs was fabricated using 0.5-μm CMOS double-poly double-metal technology. The results show that a cell is either a winner or a loser if its input voltage is larger or smaller than the other cells by 10 mV.",
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High-reliability programmable CMOS WTA/LTA circuit of O(N) complexity using a single comparator. / Hung, Y. C.; Liu, Bin-Da.

In: IEE Proceedings: Circuits, Devices and Systems, Vol. 151, No. 6, 01.12.2004, p. 579-586.

Research output: Contribution to journalArticle

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