| Original language | English |
|---|---|
| Title of host publication | 6th VLSI Design/CAD Symposium |
| Place of Publication | Chiayi |
| Pages | 136-139 |
| Publication status | Published - 1995 Aug |
High-speed C-testable bit-level systolic arrays for GF(2m) inversion
C.-T. Huang, Cheng-Wen Wu
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution