High-speed C-testable systolic array design for Galois-Field inversion

Chih Tsun Huang; Cheng Wen Wu

High-speed C-testable systolic array design for Galois-Field inversion

Chih Tsun Huang, Cheng Wen Wu

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

16 Citations (Scopus)

Abstract

Systolic architectures for inversion in Galois field (GF(2^m)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.

Original language	English
Pages (from-to)	342-346
Number of pages	5
Journal	Proceedings of European Design and Test Conference
Publication status	Published - 1997 Jan 1
Event	Proceedings of the 1997 European Design & Test Conference - Paris, Fr Duration: 1997 Mar 17 → 1997 Mar 20

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

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title = "High-speed C-testable systolic array design for Galois-Field inversion",

abstract = "Systolic architectures for inversion in Galois field (GF(2m)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.",

author = "Huang, {Chih Tsun} and Wu, {Cheng Wen}",

year = "1997",

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language = "English",

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journal = "Proceedings of European Design and Test Conference",

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T1 - High-speed C-testable systolic array design for Galois-Field inversion

AU - Huang, Chih Tsun

AU - Wu, Cheng Wen

PY - 1997/1/1

Y1 - 1997/1/1

N2 - Systolic architectures for inversion in Galois field (GF(2m)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.

AB - Systolic architectures for inversion in Galois field (GF(2m)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.

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M3 - Conference article

AN - SCOPUS:0030679131

SN - 1066-1409

SP - 342

EP - 346

JO - Proceedings of European Design and Test Conference

JF - Proceedings of European Design and Test Conference

T2 - Proceedings of the 1997 European Design & Test Conference

Y2 - 17 March 1997 through 20 March 1997

ER -

High-speed C-testable systolic array design for Galois-Field inversion

Abstract

All Science Journal Classification (ASJC) codes

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