High-speed C-testable systolic array design for Galois-Field inversion

Chih Tsun Huang, Cheng Wen Wu

Research output: Contribution to journalConference articlepeer-review

16 Citations (Scopus)

Abstract

Systolic architectures for inversion in Galois field (GF(2m)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.

Original languageEnglish
Pages (from-to)342-346
Number of pages5
JournalProceedings of European Design and Test Conference
Publication statusPublished - 1997 Jan 1
EventProceedings of the 1997 European Design & Test Conference - Paris, Fr
Duration: 1997 Mar 171997 Mar 20

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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