TY - GEN
T1 - High-speed CRC design for 10 Gbps applications
AU - Lin, Jing Shiun
AU - Lee, Chung Kung
AU - Shieh, Ming Der
AU - Chen, Jun Hong
PY - 2006/12/1
Y1 - 2006/12/1
N2 - The use of Cyclic Redundancy Codes (CRCs) in many high-throughput applications has made the design of parallel CRC circuitry an important research topic. Parallel implementation of the linear feedback shift registers (LFSRs) requires multiple input bits being processed at the same time; therefore, is much faster than the serial implementation. The common way to process M input bits simultaneously is to multiply the companion metric M times and put the resulting circuit in the feedback loop. This, however, will increase the circuit complexity within the loop so as to limit the final speedup ratio. In this paper, based on the state-space transformation, we investigate how to design high-speed CRC circuitry for 10 Gbps applications. Our design can efficiently deal with the case that the length of the message bits is not a multiple of M and achieves low-cost solution by sharing the input block with the output block outside the feedback loop.
AB - The use of Cyclic Redundancy Codes (CRCs) in many high-throughput applications has made the design of parallel CRC circuitry an important research topic. Parallel implementation of the linear feedback shift registers (LFSRs) requires multiple input bits being processed at the same time; therefore, is much faster than the serial implementation. The common way to process M input bits simultaneously is to multiply the companion metric M times and put the resulting circuit in the feedback loop. This, however, will increase the circuit complexity within the loop so as to limit the final speedup ratio. In this paper, based on the state-space transformation, we investigate how to design high-speed CRC circuitry for 10 Gbps applications. Our design can efficiently deal with the case that the length of the message bits is not a multiple of M and achieves low-cost solution by sharing the input block with the output block outside the feedback loop.
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M3 - Conference contribution
AN - SCOPUS:34547285800
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 3177
EP - 3180
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -