High-speed low-complexity implementation for data weighted averaging algorithm [ΣΔ modulator applications]

Da Huei Lee, Ching Chung Li, Tai Haur Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, a high-speed, low-complexity implementation of a data weighted averaging (DWA) algorithm is presented. Different from other published implementations, the maximum speed-limited function of the DWA algorithm, decoding for control signal generation and adding for register value updating, are replaced by carry look-ahead and rotating. Additionally, register simplification is adopted to reduce area costs. This design, in 0.25 μm CMOS, for a 3-bit 8-element example can operate at a 800 MHz clock rates for post-layout simulations, and costs only 254 transistors.

Original languageEnglish
Title of host publication2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages283-286
Number of pages4
ISBN (Electronic)0780373634, 9780780373631
DOIs
Publication statusPublished - 2002 Jan 1
Event3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan
Duration: 2002 Aug 62002 Aug 8

Publication series

Name2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
CountryTaiwan
CityTaipei
Period02-08-0602-08-08

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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