TY - GEN
T1 - High-speed modular multiplication design for public-key cryptosystems
AU - Chen, Jun Hong
AU - Lin, Wen Ching
AU - Wu, Hao Hsuan
AU - Shieh, Ming Der
PY - 2008
Y1 - 2008
N2 - Modular exponentiation for public-key cryptosystems is usually accomplished by repeated modular multiplications on large integers. A high-speed design of modular multiplication is thus very crucial to speed up the decryption/ encryption process. In this paper, we first explore how to relax the data dependency existing among the multiplication, quotient determination, and modular reduction in conventional Montgomery modular multiplication algorithm. Then we proposed a new modular reduction algorithm with a smaller critical path delay in hardware implementation. The speed improvement is achieved by reducing the critical path delay from the 4-to-2 to 3-to-2 carry-save addition, and the resulting time complexity of our development is decreased by simultaneously performing the multiplication and modular reduction processes. Experimental results show that our modular exponentiation can obtain both time and area-time (AT) advantages compared with existing work.
AB - Modular exponentiation for public-key cryptosystems is usually accomplished by repeated modular multiplications on large integers. A high-speed design of modular multiplication is thus very crucial to speed up the decryption/ encryption process. In this paper, we first explore how to relax the data dependency existing among the multiplication, quotient determination, and modular reduction in conventional Montgomery modular multiplication algorithm. Then we proposed a new modular reduction algorithm with a smaller critical path delay in hardware implementation. The speed improvement is achieved by reducing the critical path delay from the 4-to-2 to 3-to-2 carry-save addition, and the resulting time complexity of our development is decreased by simultaneously performing the multiplication and modular reduction processes. Experimental results show that our modular exponentiation can obtain both time and area-time (AT) advantages compared with existing work.
UR - http://www.scopus.com/inward/record.url?scp=51749113575&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS.2008.4541509
DO - 10.1109/ISCAS.2008.4541509
M3 - Conference contribution
AN - SCOPUS:51749113575
SN - 9781424416844
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 680
EP - 683
BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Y2 - 18 May 2008 through 21 May 2008
ER -