High throughput 2-D transform architectures for H.264 advanced video coders

Zhan Yuan Cheng, Che Hong Chen, Bin Da Liu, Jar Ferr Yang

Research output: Contribution to conferencePaperpeer-review

48 Citations (Scopus)

Abstract

In this paper, high throughput hardware architectures for fast computation of the 2-D forward, inverse and Hadamard transforms suggested in H.264 advanced video coders (AVC) are presented. After complexity and efficiency analyses, we find that the proposed architectures could provide higher throughput rate and realize in a smaller chip area than the conventional row-column approaches. The proposed architectures are synthesized with TSMC 0.35 μm technology. The synthesized multiple transform architecture could process 800 M samples/sec at 100 MHz for all three transforms.

Original languageEnglish
Pages1141-1144
Number of pages4
Publication statusPublished - 2004 Dec 1
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 2004 Dec 62004 Dec 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period04-12-0604-12-09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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