High-throughput low-cost VLSI architecture for AVC/H.264 CAVLC decoding

G. G. Lee; C. C. Lo; Y. C. Chen; H. Y. Lin; M. J. Wang

doi:10.1049/iet-ipr.2008.0064

High-throughput low-cost VLSI architecture for AVC/H.264 CAVLC decoding

G. G. Lee, C. C. Lo, Y. C. Chen, H. Y. Lin, M. J. Wang

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

This study develops a low-cost very-large-scale-integration (VLSI) hardware architecture for entropy coding with increased throughput using the statistical properties of context-based adaptive variable-length coding (CAVLC) in AVC/H.264. Statistical analyses show that better symbol length prediction was achieved by breaking the recursive dependency among codewords for the multi-symbol decoder implementation. The proposed CAVLC decoder easily meets the real-time requirements for high definition (HD) (1920×1088) applications. The clock speed is only 13 MHz under the best case scenario.

Original language	English
Article number	IIPEAT000004000002000081000001
Pages (from-to)	81-91
Number of pages	11
Journal	IET Image Processing
Volume	4
Issue number	2
DOIs	https://doi.org/10.1049/iet-ipr.2008.0064
Publication status	Published - 2010 Apr 1

All Science Journal Classification (ASJC) codes

Software
Signal Processing
Computer Vision and Pattern Recognition
Electrical and Electronic Engineering

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10.1049/iet-ipr.2008.0064

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AU - Wang, M. J.

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AB - This study develops a low-cost very-large-scale-integration (VLSI) hardware architecture for entropy coding with increased throughput using the statistical properties of context-based adaptive variable-length coding (CAVLC) in AVC/H.264. Statistical analyses show that better symbol length prediction was achieved by breaking the recursive dependency among codewords for the multi-symbol decoder implementation. The proposed CAVLC decoder easily meets the real-time requirements for high definition (HD) (1920×1088) applications. The clock speed is only 13 MHz under the best case scenario.

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High-throughput low-cost VLSI architecture for AVC/H.264 CAVLC decoding

Abstract

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