TY - JOUR
T1 - High-Throughput, power-efficient, coefficient-free and reconfigurable green design for recursive DFT in a portable DRM receiver
AU - Lai, Shin Chi
AU - Juang, Wen Ho
AU - Lin, Chen Chieh
AU - Luo, Ching Hsing
AU - Lei, Sheau-Fang
PY - 2011/6
Y1 - 2011/6
N2 - This paper presents a green design of fast recursive discrete Fourier transform (RDFT) for application to a portable DRM receiver. The proposed design has high-throughput, power-efficient, coefficient-free and reconfigurable advantages. For an audio decoder in a DRM receiver, the most computational complexity block, IMDCT algorithm, can be employed in a single hardware accelerator through this RDFT kernel to share hardware resources. Hence, the proposed design would greatly reduce the hardware costs for the realization of a portable DRM receiver. Not only do the proposed algorithms have 4 times the data throughput per transformation (DTPT) compared with the latest Lai et al. 's RDFT, but it also requires only 49.5% of computational cycles for computing all output sequences. The proposed RDFT algorithms can reduce the number of additions and multiplications by 47.5 % and 48.7%, respectively. In addition, the number of the coefficient requirements for storing cosine and sine functions can be greatly reduced by 100%. Furthermore, we realize this RDFT processor by using TMSC 0.18um 1P6M CMOS technology. The core size is 871 857 um 2 and the power consumption is 14.3mW @ 25MHz. Thus, the proposed design would be more efficient and more suitable than previous works for DRM applications.
AB - This paper presents a green design of fast recursive discrete Fourier transform (RDFT) for application to a portable DRM receiver. The proposed design has high-throughput, power-efficient, coefficient-free and reconfigurable advantages. For an audio decoder in a DRM receiver, the most computational complexity block, IMDCT algorithm, can be employed in a single hardware accelerator through this RDFT kernel to share hardware resources. Hence, the proposed design would greatly reduce the hardware costs for the realization of a portable DRM receiver. Not only do the proposed algorithms have 4 times the data throughput per transformation (DTPT) compared with the latest Lai et al. 's RDFT, but it also requires only 49.5% of computational cycles for computing all output sequences. The proposed RDFT algorithms can reduce the number of additions and multiplications by 47.5 % and 48.7%, respectively. In addition, the number of the coefficient requirements for storing cosine and sine functions can be greatly reduced by 100%. Furthermore, we realize this RDFT processor by using TMSC 0.18um 1P6M CMOS technology. The core size is 871 857 um 2 and the power consumption is 14.3mW @ 25MHz. Thus, the proposed design would be more efficient and more suitable than previous works for DRM applications.
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M3 - Article
AN - SCOPUS:84863296216
VL - 18
SP - 137
EP - 145
JO - International Journal of Electrical Engineering
JF - International Journal of Electrical Engineering
SN - 1812-3031
IS - 3
ER -