Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM

Tsai Kan Chien, Lih-Yih Chiou, Chi Shian Chang, Jing Yu Huang, Chung Han Wu, Heng Yuan Lee, Shyh Shyuan Sheu

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Among the emerging types of memory, resistive random-access memory (ReRAM) units offer faster write speeds and consume less power than those of flash memory units. With the advancement of 3-D stack technology, 3-D nonvolatile memories (NVMs) are under active development to satisfy the requirements of new applications. This brief proposes a 1.5 F2/bit nonlinear sub-teraohm vertical ReRAM (V-ReRAM) and a sensing ultrahigh-resistance read scheme that not only accurately senses sub-picoampere currents but also reduces sneak current effects. A 2-Kb V-ReRAM macro unit was fabricated using a 0.15-μ m CMOS process and the Industrial Technology Research Institute's zero-transistor-four-ReRAM V-ReRAM back-end-of-line process. The proposed read scheme increased the sensing margin by eight times when compared with the current-mirror type, a commonly used read scheme for NVMs. Additionally, the memory bit size was smaller than one-transistor-N-ReRAM V-ReRAM.

Original languageEnglish
Article number8123866
Pages (from-to)1234-1238
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume65
Issue number9
DOIs
Publication statusPublished - 2018 Sep 1

Fingerprint

Pumps
Data storage equipment
Transistors
Flash memory
Macros
Mirrors
RRAM

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Chien, Tsai Kan ; Chiou, Lih-Yih ; Chang, Chi Shian ; Huang, Jing Yu ; Wu, Chung Han ; Lee, Heng Yuan ; Sheu, Shyh Shyuan. / Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM. In: IEEE Transactions on Circuits and Systems II: Express Briefs. 2018 ; Vol. 65, No. 9. pp. 1234-1238.
@article{87bb4d2c13314b6b8a75a80eefa60a2c,
title = "Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM",
abstract = "Among the emerging types of memory, resistive random-access memory (ReRAM) units offer faster write speeds and consume less power than those of flash memory units. With the advancement of 3-D stack technology, 3-D nonvolatile memories (NVMs) are under active development to satisfy the requirements of new applications. This brief proposes a 1.5 F2/bit nonlinear sub-teraohm vertical ReRAM (V-ReRAM) and a sensing ultrahigh-resistance read scheme that not only accurately senses sub-picoampere currents but also reduces sneak current effects. A 2-Kb V-ReRAM macro unit was fabricated using a 0.15-μ m CMOS process and the Industrial Technology Research Institute's zero-transistor-four-ReRAM V-ReRAM back-end-of-line process. The proposed read scheme increased the sensing margin by eight times when compared with the current-mirror type, a commonly used read scheme for NVMs. Additionally, the memory bit size was smaller than one-transistor-N-ReRAM V-ReRAM.",
author = "Chien, {Tsai Kan} and Lih-Yih Chiou and Chang, {Chi Shian} and Huang, {Jing Yu} and Wu, {Chung Han} and Lee, {Heng Yuan} and Sheu, {Shyh Shyuan}",
year = "2018",
month = "9",
day = "1",
doi = "10.1109/TCSII.2017.2778246",
language = "English",
volume = "65",
pages = "1234--1238",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-7747",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM. / Chien, Tsai Kan; Chiou, Lih-Yih; Chang, Chi Shian; Huang, Jing Yu; Wu, Chung Han; Lee, Heng Yuan; Sheu, Shyh Shyuan.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, No. 9, 8123866, 01.09.2018, p. 1234-1238.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM

AU - Chien, Tsai Kan

AU - Chiou, Lih-Yih

AU - Chang, Chi Shian

AU - Huang, Jing Yu

AU - Wu, Chung Han

AU - Lee, Heng Yuan

AU - Sheu, Shyh Shyuan

PY - 2018/9/1

Y1 - 2018/9/1

N2 - Among the emerging types of memory, resistive random-access memory (ReRAM) units offer faster write speeds and consume less power than those of flash memory units. With the advancement of 3-D stack technology, 3-D nonvolatile memories (NVMs) are under active development to satisfy the requirements of new applications. This brief proposes a 1.5 F2/bit nonlinear sub-teraohm vertical ReRAM (V-ReRAM) and a sensing ultrahigh-resistance read scheme that not only accurately senses sub-picoampere currents but also reduces sneak current effects. A 2-Kb V-ReRAM macro unit was fabricated using a 0.15-μ m CMOS process and the Industrial Technology Research Institute's zero-transistor-four-ReRAM V-ReRAM back-end-of-line process. The proposed read scheme increased the sensing margin by eight times when compared with the current-mirror type, a commonly used read scheme for NVMs. Additionally, the memory bit size was smaller than one-transistor-N-ReRAM V-ReRAM.

AB - Among the emerging types of memory, resistive random-access memory (ReRAM) units offer faster write speeds and consume less power than those of flash memory units. With the advancement of 3-D stack technology, 3-D nonvolatile memories (NVMs) are under active development to satisfy the requirements of new applications. This brief proposes a 1.5 F2/bit nonlinear sub-teraohm vertical ReRAM (V-ReRAM) and a sensing ultrahigh-resistance read scheme that not only accurately senses sub-picoampere currents but also reduces sneak current effects. A 2-Kb V-ReRAM macro unit was fabricated using a 0.15-μ m CMOS process and the Industrial Technology Research Institute's zero-transistor-four-ReRAM V-ReRAM back-end-of-line process. The proposed read scheme increased the sensing margin by eight times when compared with the current-mirror type, a commonly used read scheme for NVMs. Additionally, the memory bit size was smaller than one-transistor-N-ReRAM V-ReRAM.

UR - http://www.scopus.com/inward/record.url?scp=85037617262&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85037617262&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2017.2778246

DO - 10.1109/TCSII.2017.2778246

M3 - Article

VL - 65

SP - 1234

EP - 1238

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-7747

IS - 9

M1 - 8123866

ER -